From 6c7d19f91734af088fb634e8f60b416f8afb0bc8 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 14 Nov 2021 10:36:26 +0000
Subject: [PATCH]

---
 docs/pinmux.mdwn | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn
index d51b49b90..5996adfa4 100644
--- a/docs/pinmux.mdwn
+++ b/docs/pinmux.mdwn
@@ -1,5 +1,10 @@
 # Pinmux, IO Pads, and JTAG Boundary scan
 
+Links:
+
+* <http://www2.eng.cam.ac.uk/~dmh/4b7/resource/section14.htm>
+* <https://ftp.libre-soc.org/Pin_Control_Subsystem_Overview.pdf>
+
 Managing IO on an ASIC is nowhere near as simple as on an FPGA.
 An FPGA has built-in IO Pads, the wires terminate inside an
 existing silicon block which has been tested for you.  In an
-- 
2.30.2