From 6c7dad6aef97109e5427e5a46f63c36c3ad20585 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 11 Oct 2023 11:57:58 +0100 Subject: [PATCH] accidentally commented-out matrix tests --- src/openpower/decoder/isa/test_caller_svp64_matrix.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py index 579617b9..aa6401aa 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py +++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py @@ -16,7 +16,7 @@ class DecoderTestCase(FHDLTestCase): for i in range(32): self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) - def tst_sv_remap1(self): + def test_sv_remap1(self): """>>> lst = ["svshape 2, 2, 3, 0, 0", "svremap 31, 1, 2, 3, 0, 0, 0", "sv.fmadds *0, *8, *16, *0" @@ -81,7 +81,7 @@ class DecoderTestCase(FHDLTestCase): # self.assertEqual(sim.fpr(i+2), t) # self.assertEqual(sim.fpr(i+6), u) - def tst_sv_remap2(self): + def test_sv_remap2(self): """>>> lst = ["svshape 5, 4, 3, 0, 0", "svremap 31, 1, 2, 3, 0, 0, 0", "sv.fmadds *0, *8, *16, *0" -- 2.30.2