From 6c8237b10f5fbff1cde21a3f933adb3ac3f72853 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 20 Sep 2022 12:11:57 +0100 Subject: [PATCH] sort specifiers in pysvp64dis in lexicographical order --- src/openpower/decoder/power_insn.py | 1 + src/openpower/sv/trans/test_pysvp64dis.py | 20 ++++++++++---------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index 600d8fd4..94aa8f57 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -1971,6 +1971,7 @@ class SVP64Instruction(PrefixedInstruction): # convert specifiers to /x/y/z specifiers = list(rm.specifiers(record=record)) + specifiers.sort() # sort lexicographically if specifiers: # if any add one extra to get the extra "/" specifiers = ([""] + specifiers) specifiers = "/".join(specifiers) diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py index 7b05af6e..c44d2511 100644 --- a/src/openpower/sv/trans/test_pysvp64dis.py +++ b/src/openpower/sv/trans/test_pysvp64dis.py @@ -242,8 +242,8 @@ class SVSTATETestCase(unittest.TestCase): "sv.add./m=lt *3,*7,*11", "sv.add. *3,*7,*11", "sv.extsw/m=r30 3,7", - "sv.extsw/sm=r30/dm=~r30 3,7", - "sv.extsw/sm=gt/dm=eq 3,7", + "sv.extsw/dm=~r30/sm=r30 3,7", + "sv.extsw/dm=eq/sm=gt 3,7", "sv.extsw/sm=~r3 3,7", "sv.extsw/dm=r30 3,7", ] @@ -283,14 +283,14 @@ class SVSTATETestCase(unittest.TestCase): "sv.bc/m=r3/snz 12,*1,0xc", "sv.bc/m=r3/sz 12,*1,0xc", "sv.bc/all/sl/slu 12,*1,0xc", - "sv.bc/all/snz/sl/slu/lru 12,*1,0xc", - "sv.bc/vs/all/snz/sl/slu/lru 12,*1,0xc", - "sv.bc/vsi/all/snz/sl/slu/lru 12,*1,0xc", - "sv.bc/vsb/all/snz/sl/slu/lru 12,*1,0xc", - "sv.bc/vsbi/all/snz/sl/slu/lru 12,*1,0xc", - "sv.bc/ctr/all/snz/sl/slu/lru 12,*1,0xc", - "sv.bc/cti/all/snz/sl/slu/lru 12,*1,0xc", - "sv.bc/vsb/ctr/all/snz/sl/slu/lru 12,*1,0xc", + "sv.bc/all/lru/sl/slu/snz 12,*1,0xc", + "sv.bc/all/lru/sl/slu/snz/vs 12,*1,0xc", + "sv.bc/all/lru/sl/slu/snz/vsi 12,*1,0xc", + "sv.bc/all/lru/sl/slu/snz/vsb 12,*1,0xc", + "sv.bc/all/lru/sl/slu/snz/vsbi 12,*1,0xc", + "sv.bc/all/ctr/lru/snz/sl/slu 12,*1,0xc", + "sv.bc/all/cti/sl/slu/lru/snz 12,*1,0xc", + "sv.bc/all/ctr/sl/slu/lru/snz/vsb 12,*1,0xc", ] self._do_tst(expected) -- 2.30.2