From 6c825cd46bac36333c1970c549a8630f8c850794 Mon Sep 17 00:00:00 2001 From: David Sherwood Date: Mon, 17 Aug 2015 11:06:34 +0000 Subject: [PATCH] arm.c (neon_element_bits): Replace call to GET_MODE_BITSIZE (GET_MODE_INNER (m)) with... * config/arm/arm.c (neon_element_bits): Replace call to GET_MODE_BITSIZE (GET_MODE_INNER (m)) with GET_MODE_UNIT_BITSIZE (m). * config/arm/neon.md (neon_vget_lane): Likewise. (neon_vget_laneu, neon_vset_lane): Likewise (neon_vdup_lane): Likewise. * config/i386/i386.c (ix86_expand_int_vcond): Likewise. (ix86_expand_multi_arg_builtin, ix86_expand_reduc): Likewise. (expand_vec_perm_palignr, ix86_expand_sse2_abs): Likewise. * config/rs6000/rs6000.c (rs6000_do_expand_vec_perm): Likewise. * config/spu/spu.c (arith_immediate_p): Likewise. * expmed.c (store_bit_field_1, extract_bit_field_1): Likewise. * expr.c (expand_expr_real_2): Likewise. * optabs.c (shift_amt_for_vec_perm_mask): Likewise. * simplify-rtx.c (simplify_immed_subreg): Likewise. * tree-cfg.c (verify_gimple_assign_ternary): Likewise. * tree-vect-patterns.c (vect_recog_mixed_size_cond_pattern): Likewise. New variable. * fold-const.c (fold_binary_loc): Replace call to GET_MODE_PRECISION (GET_MODE_INNER (m)) with GET_MODE_UNIT_PRECISION (m). From-SVN: r226936 --- gcc/ChangeLog | 23 +++++++++++++++++++++++ gcc/config/arm/arm.c | 2 +- gcc/config/arm/neon.md | 12 ++++++------ gcc/config/i386/i386.c | 13 ++++++------- gcc/config/rs6000/rs6000.c | 3 +-- gcc/config/spu/spu.c | 2 +- gcc/expmed.c | 8 ++++---- gcc/expr.c | 2 +- gcc/fold-const.c | 2 +- gcc/optabs.c | 2 +- gcc/simplify-rtx.c | 2 +- gcc/tree-cfg.c | 6 ++---- gcc/tree-vect-patterns.c | 13 +++++++------ 13 files changed, 55 insertions(+), 35 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 66bfd50a546..76d1d07043b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,26 @@ +2015-08-17 David Sherwood + + * config/arm/arm.c (neon_element_bits): Replace call to + GET_MODE_BITSIZE (GET_MODE_INNER (m)) with GET_MODE_UNIT_BITSIZE (m). + * config/arm/neon.md (neon_vget_lane): Likewise. + (neon_vget_laneu, neon_vset_lane): Likewise + (neon_vdup_lane): Likewise. + * config/i386/i386.c (ix86_expand_int_vcond): Likewise. + (ix86_expand_multi_arg_builtin, ix86_expand_reduc): Likewise. + (expand_vec_perm_palignr, ix86_expand_sse2_abs): Likewise. + * config/rs6000/rs6000.c (rs6000_do_expand_vec_perm): Likewise. + * config/spu/spu.c (arith_immediate_p): Likewise. + * expmed.c (store_bit_field_1, extract_bit_field_1): Likewise. + * expr.c (expand_expr_real_2): Likewise. + * optabs.c (shift_amt_for_vec_perm_mask): Likewise. + * simplify-rtx.c (simplify_immed_subreg): Likewise. + * tree-cfg.c (verify_gimple_assign_ternary): Likewise. + * tree-vect-patterns.c (vect_recog_mixed_size_cond_pattern): Likewise. + New variable. + * fold-const.c (fold_binary_loc): Replace call to + GET_MODE_PRECISION (GET_MODE_INNER (m)) with + GET_MODE_UNIT_PRECISION (m). + 2015-08-17 Mike Stump * config/arm/arm.c (arm_block_move_unaligned_straight): diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 8ded4946a6a..57702cbc8de 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -12836,7 +12836,7 @@ neon_const_bounds (rtx operand, HOST_WIDE_INT low, HOST_WIDE_INT high) HOST_WIDE_INT neon_element_bits (machine_mode mode) { - return GET_MODE_BITSIZE (GET_MODE_INNER (mode)); + return GET_MODE_UNIT_BITSIZE (mode); } diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index b1bf26a9451..873330fc7de 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -2672,12 +2672,12 @@ to this model. */ unsigned int elt = INTVAL (operands[2]); unsigned int reg_nelts - = 64 / GET_MODE_BITSIZE (GET_MODE_INNER (mode)); + = 64 / GET_MODE_UNIT_BITSIZE (mode); elt ^= reg_nelts - 1; operands[2] = GEN_INT (elt); } - if (GET_MODE_BITSIZE (GET_MODE_INNER (mode)) == 32) + if (GET_MODE_UNIT_BITSIZE (mode) == 32) emit_insn (gen_vec_extract (operands[0], operands[1], operands[2])); else emit_insn (gen_neon_vget_lane_sext_internal (operands[0], @@ -2701,12 +2701,12 @@ to this model. */ unsigned int elt = INTVAL (operands[2]); unsigned int reg_nelts - = 64 / GET_MODE_BITSIZE (GET_MODE_INNER (mode)); + = 64 / GET_MODE_UNIT_BITSIZE (mode); elt ^= reg_nelts - 1; operands[2] = GEN_INT (elt); } - if (GET_MODE_BITSIZE (GET_MODE_INNER (mode)) == 32) + if (GET_MODE_UNIT_BITSIZE (mode) == 32) emit_insn (gen_vec_extract (operands[0], operands[1], operands[2])); else emit_insn (gen_neon_vget_lane_zext_internal (operands[0], @@ -2766,7 +2766,7 @@ if (BYTES_BIG_ENDIAN) if (BYTES_BIG_ENDIAN) { unsigned int reg_nelts - = 64 / GET_MODE_BITSIZE (GET_MODE_INNER (mode)); + = 64 / GET_MODE_UNIT_BITSIZE (mode); elt ^= reg_nelts - 1; } @@ -2869,7 +2869,7 @@ if (BYTES_BIG_ENDIAN) { unsigned int elt = INTVAL (operands[2]); unsigned int reg_nelts - = 64 / GET_MODE_BITSIZE (GET_MODE_INNER (mode)); + = 64 / GET_MODE_UNIT_BITSIZE (mode); elt ^= reg_nelts - 1; operands[2] = GEN_INT (elt); } diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 4a0986c7f88..51eca5269b4 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -21789,7 +21789,7 @@ ix86_expand_int_vcond (rtx operands[]) || (TARGET_AVX2 && GET_MODE_SIZE (data_mode) == 32))) { rtx negop = operands[2 - (code == LT)]; - int shift = GET_MODE_BITSIZE (GET_MODE_INNER (data_mode)) - 1; + int shift = GET_MODE_UNIT_BITSIZE (data_mode) - 1; if (negop == CONST1_RTX (data_mode)) { rtx res = expand_simple_binop (mode, LSHIFTRT, cop0, GEN_INT (shift), @@ -36227,7 +36227,7 @@ ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target, xop_rotl: if (CONST_INT_P (op)) { - int mask = GET_MODE_BITSIZE (GET_MODE_INNER (tmode)) - 1; + int mask = GET_MODE_UNIT_BITSIZE (tmode) - 1; op = GEN_INT (INTVAL (op) & mask); gcc_checking_assert (insn_data[icode].operand[i + 1].predicate (op, mode)); @@ -45571,12 +45571,12 @@ ix86_expand_reduc (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in) } for (i = GET_MODE_BITSIZE (mode); - i > GET_MODE_BITSIZE (GET_MODE_INNER (mode)); + i > GET_MODE_UNIT_BITSIZE (mode); i >>= 1) { half = gen_reg_rtx (mode); emit_reduc_half (half, vec, i); - if (i == GET_MODE_BITSIZE (GET_MODE_INNER (mode)) * 2) + if (i == GET_MODE_UNIT_BITSIZE (mode) * 2) dst = dest; else dst = gen_reg_rtx (mode); @@ -47959,7 +47959,7 @@ expand_vec_perm_palignr (struct expand_vec_perm_d *d, bool single_insn_only_p) return expand_vec_perm_1 (&dcopy); } - shift = GEN_INT (min * GET_MODE_BITSIZE (GET_MODE_INNER (d->vmode))); + shift = GEN_INT (min * GET_MODE_UNIT_BITSIZE (d->vmode)); if (GET_MODE_SIZE (d->vmode) == 16) { target = gen_reg_rtx (TImode); @@ -50409,8 +50409,7 @@ ix86_expand_sse2_abs (rtx target, rtx input) value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */ case V4SImode: tmp0 = expand_simple_binop (mode, ASHIFTRT, input, - GEN_INT (GET_MODE_BITSIZE - (GET_MODE_INNER (mode)) - 1), + GEN_INT (GET_MODE_UNIT_BITSIZE (mode) - 1), NULL, 0, OPTAB_DIRECT); tmp1 = expand_simple_binop (mode, XOR, tmp0, input, NULL, 0, OPTAB_DIRECT); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index d1326eba47d..2a969782f26 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -32340,8 +32340,7 @@ rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1, imode = vmode; if (GET_MODE_CLASS (vmode) != MODE_VECTOR_INT) { - imode = GET_MODE_INNER (vmode); - imode = mode_for_size (GET_MODE_BITSIZE (imode), MODE_INT, 0); + imode = mode_for_size (GET_MODE_UNIT_BITSIZE (vmode), MODE_INT, 0); imode = mode_for_vector (imode, nelt); } diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c index f51dd4364c6..ca762877a0f 100644 --- a/gcc/config/spu/spu.c +++ b/gcc/config/spu/spu.c @@ -3392,7 +3392,7 @@ arith_immediate_p (rtx op, machine_mode mode, constant_to_array (mode, op, arr); bytes = GET_MODE_UNIT_SIZE (mode); - mode = mode_for_size (GET_MODE_BITSIZE (GET_MODE_INNER (mode)), MODE_INT, 0); + mode = mode_for_size (GET_MODE_UNIT_BITSIZE (mode), MODE_INT, 0); /* Check that bytes are repeated. */ for (i = bytes; i < 16; i += bytes) diff --git a/gcc/expmed.c b/gcc/expmed.c index 3c70cdece38..59b2919ee3a 100644 --- a/gcc/expmed.c +++ b/gcc/expmed.c @@ -680,8 +680,8 @@ store_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize, && !MEM_P (op0) && optab_handler (vec_set_optab, GET_MODE (op0)) != CODE_FOR_nothing && fieldmode == GET_MODE_INNER (GET_MODE (op0)) - && bitsize == GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0))) - && !(bitnum % GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0))))) + && bitsize == GET_MODE_UNIT_BITSIZE (GET_MODE (op0)) + && !(bitnum % GET_MODE_UNIT_BITSIZE (GET_MODE (op0)))) { struct expand_operand ops[3]; machine_mode outermode = GET_MODE (op0); @@ -1491,8 +1491,8 @@ extract_bit_field_1 (rtx str_rtx, unsigned HOST_WIDE_INT bitsize, if (VECTOR_MODE_P (GET_MODE (op0)) && !MEM_P (op0) && optab_handler (vec_extract_optab, GET_MODE (op0)) != CODE_FOR_nothing - && ((bitnum + bitsize - 1) / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0))) - == bitnum / GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (op0))))) + && ((bitnum + bitsize - 1) / GET_MODE_UNIT_BITSIZE (GET_MODE (op0)) + == bitnum / GET_MODE_UNIT_BITSIZE (GET_MODE (op0)))) { struct expand_operand ops[3]; machine_mode outermode = GET_MODE (op0); diff --git a/gcc/expr.c b/gcc/expr.c index f604f5251cf..3202f555838 100644 --- a/gcc/expr.c +++ b/gcc/expr.c @@ -9008,7 +9008,7 @@ expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode, little-endian, or element N-1 if big-endian. So pull the scalar result out of that element. */ int index = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (vec_mode) - 1 : 0; - int bitsize = GET_MODE_BITSIZE (GET_MODE_INNER (vec_mode)); + int bitsize = GET_MODE_UNIT_BITSIZE (vec_mode); temp = extract_bit_field (temp, bitsize, bitsize * index, unsignedp, target, mode, mode); gcc_assert (temp); diff --git a/gcc/fold-const.c b/gcc/fold-const.c index 6c65fe1c786..93d65147dd1 100644 --- a/gcc/fold-const.c +++ b/gcc/fold-const.c @@ -9421,7 +9421,7 @@ fold_binary_loc (location_t loc, /* Only create rotates in complete modes. Other cases are not expanded properly. */ && (element_precision (rtype) - == GET_MODE_PRECISION (GET_MODE_INNER (TYPE_MODE (rtype))))) + == GET_MODE_UNIT_PRECISION (TYPE_MODE (rtype)))) { tree tree01, tree11; enum tree_code code01, code11; diff --git a/gcc/optabs.c b/gcc/optabs.c index a6ca706a170..97c1d387672 100644 --- a/gcc/optabs.c +++ b/gcc/optabs.c @@ -6588,7 +6588,7 @@ static rtx shift_amt_for_vec_perm_mask (rtx sel) { unsigned int i, first, nelt = GET_MODE_NUNITS (GET_MODE (sel)); - unsigned int bitsize = GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (sel))); + unsigned int bitsize = GET_MODE_UNIT_BITSIZE (GET_MODE (sel)); if (GET_CODE (sel) != CONST_VECTOR) return NULL_RTX; diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c index ad003d83cd5..f9352a180e4 100644 --- a/gcc/simplify-rtx.c +++ b/gcc/simplify-rtx.c @@ -5491,7 +5491,7 @@ simplify_immed_subreg (machine_mode outermode, rtx op, { num_elem = CONST_VECTOR_NUNITS (op); elems = &CONST_VECTOR_ELT (op, 0); - elem_bitsize = GET_MODE_BITSIZE (GET_MODE_INNER (innermode)); + elem_bitsize = GET_MODE_UNIT_BITSIZE (innermode); } else { diff --git a/gcc/tree-cfg.c b/gcc/tree-cfg.c index 588ab69b24e..416c816fb5f 100644 --- a/gcc/tree-cfg.c +++ b/gcc/tree-cfg.c @@ -4052,10 +4052,8 @@ verify_gimple_assign_ternary (gassign *stmt) case SAD_EXPR: if (!useless_type_conversion_p (rhs1_type, rhs2_type) || !useless_type_conversion_p (lhs_type, rhs3_type) - || 2 * GET_MODE_BITSIZE (GET_MODE_INNER - (TYPE_MODE (TREE_TYPE (rhs1_type)))) - > GET_MODE_BITSIZE (GET_MODE_INNER - (TYPE_MODE (TREE_TYPE (lhs_type))))) + || 2 * GET_MODE_UNIT_BITSIZE (TYPE_MODE (TREE_TYPE (rhs1_type))) + > GET_MODE_UNIT_BITSIZE (TYPE_MODE (TREE_TYPE (lhs_type)))) { error ("type mismatch in sad expression"); debug_generic_expr (lhs_type); diff --git a/gcc/tree-vect-patterns.c b/gcc/tree-vect-patterns.c index bc3117d0ad2..758ca3875f8 100644 --- a/gcc/tree-vect-patterns.c +++ b/gcc/tree-vect-patterns.c @@ -2784,7 +2784,6 @@ vect_recog_mixed_size_cond_pattern (vec *stmts, tree *type_in, tree cond_expr, then_clause, else_clause; stmt_vec_info stmt_vinfo = vinfo_for_stmt (last_stmt), def_stmt_info; tree type, vectype, comp_vectype, itype = NULL_TREE, vecitype; - machine_mode cmpmode; gimple pattern_stmt, def_stmt; loop_vec_info loop_vinfo = STMT_VINFO_LOOP_VINFO (stmt_vinfo); bb_vec_info bb_vinfo = STMT_VINFO_BB_VINFO (stmt_vinfo); @@ -2846,9 +2845,11 @@ vect_recog_mixed_size_cond_pattern (vec *stmts, tree *type_in, itype = orig_type1; } - cmpmode = GET_MODE_INNER (TYPE_MODE (comp_vectype)); - if (GET_MODE_BITSIZE (TYPE_MODE (type)) == GET_MODE_BITSIZE (cmpmode)) + HOST_WIDE_INT cmp_mode_size + = GET_MODE_UNIT_BITSIZE (TYPE_MODE (comp_vectype)); + + if (GET_MODE_BITSIZE (TYPE_MODE (type)) == cmp_mode_size) return NULL; vectype = get_vectype_for_scalar_type (type); @@ -2859,11 +2860,11 @@ vect_recog_mixed_size_cond_pattern (vec *stmts, tree *type_in, return NULL; if (itype == NULL_TREE) - itype = build_nonstandard_integer_type (GET_MODE_BITSIZE (cmpmode), + itype = build_nonstandard_integer_type (cmp_mode_size, TYPE_UNSIGNED (type)); if (itype == NULL_TREE - || GET_MODE_BITSIZE (TYPE_MODE (itype)) != GET_MODE_BITSIZE (cmpmode)) + || GET_MODE_BITSIZE (TYPE_MODE (itype)) != cmp_mode_size) return NULL; vecitype = get_vectype_for_scalar_type (itype); @@ -2873,7 +2874,7 @@ vect_recog_mixed_size_cond_pattern (vec *stmts, tree *type_in, if (!expand_vec_cond_expr_p (vecitype, comp_vectype)) return NULL; - if (GET_MODE_BITSIZE (TYPE_MODE (type)) > GET_MODE_BITSIZE (cmpmode)) + if (GET_MODE_BITSIZE (TYPE_MODE (type)) > cmp_mode_size) { if ((TREE_CODE (then_clause) == INTEGER_CST && !int_fits_type_p (then_clause, itype)) -- 2.30.2