From 6c9aef6f6baeed83b07c25eba57b87a15a6db95c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 27 May 2020 00:47:53 +0100 Subject: [PATCH] check assertions --- src/soc/regfile/virtual_port.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/regfile/virtual_port.py b/src/soc/regfile/virtual_port.py index 152fb4cd..322efe8e 100644 --- a/src/soc/regfile/virtual_port.py +++ b/src/soc/regfile/virtual_port.py @@ -92,9 +92,10 @@ def regfile_array_sim(dut, rp1, rp2, rp3, wp): yield rp2.ren.eq(0) data1 = yield rp1.data_o print (data1) + assert data1 == 6, data1 data2 = yield rp2.data_o print (data2) - assert data1 == 6 + assert data2 == 2, data2 yield data = yield rp1.data_o print (data) -- 2.30.2