From 6cbd1d16921c5336e87e7d954e7ac6da67749ba9 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Fri, 6 Apr 2018 11:44:59 -0700 Subject: [PATCH] iris: binders --- src/gallium/drivers/iris/iris_binder.c | 58 +++++++++++++++++++++++++ src/gallium/drivers/iris/iris_binder.h | 47 ++++++++++++++++++++ src/gallium/drivers/iris/iris_bufmgr.c | 9 +++- src/gallium/drivers/iris/iris_bufmgr.h | 3 ++ src/gallium/drivers/iris/iris_context.c | 3 ++ src/gallium/drivers/iris/iris_context.h | 3 +- src/gallium/drivers/iris/iris_state.c | 39 ++++++++++++----- src/gallium/drivers/iris/meson.build | 2 + 8 files changed, 151 insertions(+), 13 deletions(-) create mode 100644 src/gallium/drivers/iris/iris_binder.c create mode 100644 src/gallium/drivers/iris/iris_binder.h diff --git a/src/gallium/drivers/iris/iris_binder.c b/src/gallium/drivers/iris/iris_binder.c new file mode 100644 index 00000000000..5c54c0a13d9 --- /dev/null +++ b/src/gallium/drivers/iris/iris_binder.c @@ -0,0 +1,58 @@ +/* + * Copyright © 2018 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * on the rights to use, copy, modify, merge, publish, distribute, sub + * license, and/or sell copies of the Software, and to permit persons to whom + * the Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "util/u_math.h" +#include "iris_binder.h" +#include "iris_bufmgr.h" + +/* 64kb */ +#define BINDER_SIZE (64 * 1024) + +void * +iris_binder_reserve(struct iris_binder *binder, unsigned size, + uint32_t *out_offset) +{ + /* XXX: Implement a real ringbuffer, for now just croak if run out */ + assert(size > 0); + assert(binder->insert_point + size <= BINDER_SIZE); + + binder->insert_point = align(binder->insert_point + size, 64); + + return binder->map + *out_offset; +} + +void +iris_init_binder(struct iris_binder *binder, struct iris_bufmgr *bufmgr) +{ + binder->bo = + iris_bo_alloc(bufmgr, "binder", BINDER_SIZE, IRIS_MEMZONE_BINDER); + binder->map = iris_bo_map(NULL, binder->bo, MAP_WRITE); +} + +void +iris_destroy_binder(struct iris_binder *binder) +{ + iris_bo_unreference(binder->bo); + free(binder); +} diff --git a/src/gallium/drivers/iris/iris_binder.h b/src/gallium/drivers/iris/iris_binder.h new file mode 100644 index 00000000000..5830288b5c5 --- /dev/null +++ b/src/gallium/drivers/iris/iris_binder.h @@ -0,0 +1,47 @@ +/* + * Copyright © 2018 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef IRIS_BINDER_DOT_H +#define IRIS_BINDER_DOT_H + +#include +#include + +struct iris_bo; +struct iris_bufmgr; + +struct iris_binder +{ + struct iris_bo *bo; + void *map; + + /* Insert new entries at this offset (in bytes) */ + unsigned insert_point; +}; + +void iris_init_binder(struct iris_binder *binder, struct iris_bufmgr *bufmgr); +void iris_destroy_binder(struct iris_binder *binder); +void *iris_binder_reserve(struct iris_binder *binder, unsigned size, + uint32_t *out_offset); + +#endif diff --git a/src/gallium/drivers/iris/iris_bufmgr.c b/src/gallium/drivers/iris/iris_bufmgr.c index 6423136dd4d..c1a4fa5d5f3 100644 --- a/src/gallium/drivers/iris/iris_bufmgr.c +++ b/src/gallium/drivers/iris/iris_bufmgr.c @@ -236,9 +236,13 @@ memzone_for_address(uint64_t address) if (address >= 2 * _4GB) return IRIS_MEMZONE_DYNAMIC; - if (address >= 1 * _4GB) + if (address > 1 * _4GB) return IRIS_MEMZONE_SURFACE; + /* The binder isn't in any memory zone. */ + if (address == 1 * _4GB) + return IRIS_MEMZONE_BINDER; + return IRIS_MEMZONE_SHADER; } @@ -336,6 +340,9 @@ vma_alloc(struct iris_bufmgr *bufmgr, uint64_t size, uint64_t alignment) { + if (memzone == IRIS_MEMZONE_BINDER) + return 1ull << 32; + struct bo_cache_bucket *bucket = get_bucket_allocator(bufmgr, size); if (bucket) diff --git a/src/gallium/drivers/iris/iris_bufmgr.h b/src/gallium/drivers/iris/iris_bufmgr.h index febecd95ed1..eb2148da3f5 100644 --- a/src/gallium/drivers/iris/iris_bufmgr.h +++ b/src/gallium/drivers/iris/iris_bufmgr.h @@ -41,8 +41,11 @@ enum iris_memory_zone { IRIS_MEMZONE_SURFACE, IRIS_MEMZONE_SHADER, IRIS_MEMZONE_OTHER, + + IRIS_MEMZONE_BINDER, }; +/* Intentionally exclude IRIS_MEMZONE_BINDER */ #define IRIS_MEMZONE_COUNT (IRIS_MEMZONE_OTHER + 1) struct iris_bo { diff --git a/src/gallium/drivers/iris/iris_context.c b/src/gallium/drivers/iris/iris_context.c index d0656cf2f22..dbf4759c96b 100644 --- a/src/gallium/drivers/iris/iris_context.c +++ b/src/gallium/drivers/iris/iris_context.c @@ -80,6 +80,7 @@ iris_destroy_context(struct pipe_context *ctx) u_upload_destroy(ctx->stream_uploader); iris_destroy_program_cache(ice); + iris_destroy_binder(&ice->state.binder); u_upload_destroy(ice->state.surface_uploader); u_upload_destroy(ice->state.dynamic_uploader); @@ -136,6 +137,8 @@ iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags) iris_init_program_cache(ice); + iris_init_binder(&ice->state.binder, screen->bufmgr); + ice->state.surface_uploader = u_upload_create(&ice->ctx, 16384, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE, IRIS_RESOURCE_FLAG_SURFACE_MEMZONE); diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h index e0cdcb765ed..51eabf91e4b 100644 --- a/src/gallium/drivers/iris/iris_context.h +++ b/src/gallium/drivers/iris/iris_context.h @@ -29,10 +29,10 @@ #include "intel/common/gen_debug.h" #include "intel/compiler/brw_compiler.h" #include "iris_batch.h" +#include "iris_binder.h" #include "iris_screen.h" struct iris_bo; -struct iris_batch; #define IRIS_RESOURCE_FLAG_SHADER_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 0) #define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1) @@ -185,6 +185,7 @@ struct iris_context { struct iris_sampler_state *samplers[MESA_SHADER_STAGES][IRIS_MAX_TEXTURE_SAMPLERS]; + struct iris_binder binder; struct u_upload_mgr *surface_uploader; struct u_upload_mgr *dynamic_uploader; diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 2a76873c91e..671b1e723f8 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -57,10 +57,15 @@ static uint64_t __gen_combine_address(struct iris_batch *batch, void *location, struct iris_address addr, uint32_t delta) { - if (addr.bo) + uint64_t result = addr.offset + delta; + + if (addr.bo) { iris_use_pinned_bo(batch, addr.bo, addr.write); + /* Assume this is a general address, not relative to a base. */ + result += addr.bo->gtt_offset; + } - return addr.offset + delta; + return result; } #define __genxml_cmd_length(cmd) cmd ## _length @@ -279,13 +284,22 @@ stream_state(struct iris_batch *batch, struct u_upload_mgr *uploader, unsigned size, unsigned alignment, - unsigned *out_offset) + uint32_t *out_offset) { struct pipe_resource *res = NULL; void *ptr = NULL; u_upload_alloc(uploader, 0, size, alignment, out_offset, &res, &ptr); - iris_use_pinned_bo(batch, ((struct iris_resource *) res)->bo, false); + + struct iris_bo *bo = ((struct iris_resource *) res)->bo; + iris_use_pinned_bo(batch, bo, false); + + /* Compute an offset from state base address. It's a 4GB region starting + * at 0GB, 4GB, or 8GB, so we can simply drop everything above 32 bits. + */ + assert(bo->gtt_offset < 3 * (1ull << 32)); + *out_offset += bo->gtt_offset & ((1ull << 32) - 1); + pipe_resource_reference(&res, NULL); return ptr; @@ -906,8 +920,8 @@ iris_create_sampler_view(struct pipe_context *ctx, isl_surf_fill_state(&screen->isl_dev, isv->surface_state, .surf = &itex->surf, .view = &isv->view, - .mocs = MOCS_WB); - // .address = ... + .mocs = MOCS_WB, + .address = itex->bo->gtt_offset); // .aux_surf = // .clear_color = clear_color, @@ -957,8 +971,8 @@ iris_create_surface(struct pipe_context *ctx, isl_surf_fill_state(&screen->isl_dev, surf->surface_state, .surf = &itex->surf, .view = &surf->view, - .mocs = MOCS_WB); - // .address = ... + .mocs = MOCS_WB, + .address = itex->bo->gtt_offset); // .aux_surf = // .clear_color = clear_color, @@ -1954,9 +1968,9 @@ iris_upload_render_state(struct iris_context *ice, uint32_t *bt_map = NULL; if (prog_data->binding_table.size_bytes != 0) { - bt_map = stream_state(batch, ice->state.surface_uploader, - prog_data->binding_table.size_bytes, - 64, &bt_offset); + bt_map = iris_binder_reserve(&ice->state.binder, + prog_data->binding_table.size_bytes, + &bt_offset); } iris_emit_cmd(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS), ptr) { @@ -1973,6 +1987,9 @@ iris_upload_render_state(struct iris_context *ice, struct iris_surface *surf = (void *) cso_fb->cbufs[i]; struct iris_resource *res = (void *) surf->pipe.texture; iris_use_pinned_bo(batch, res->bo, true); + /* emit_state already adjusts for surface base address, so + * it already basically subtracts the binder address for us. + */ *bt_map++ = emit_state(batch, ice->state.surface_uploader, surf->surface_state, diff --git a/src/gallium/drivers/iris/meson.build b/src/gallium/drivers/iris/meson.build index af8bbcfe758..0bd8403cf2a 100644 --- a/src/gallium/drivers/iris/meson.build +++ b/src/gallium/drivers/iris/meson.build @@ -21,6 +21,8 @@ files_libiris = files( 'iris_batch.c', 'iris_batch.h', + 'iris_binder.c', + 'iris_binder.h', 'iris_blit.c', 'iris_bufmgr.c', 'iris_bufmgr.h', -- 2.30.2