From 6d174c79031573f9fa3e213d237c81b9fd0b5bbd Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 2 Jul 2022 17:37:47 +0100 Subject: [PATCH] setvl has new CTR mode, making room in encoding needed fixing unit tests --- openpower/isa/simplev.mdwn | 28 +++++----- .../decoder/isa/test_caller_setvl.py | 55 +++++++++++++------ .../decoder/isa/test_caller_svstate.py | 9 ++- 3 files changed, 58 insertions(+), 34 deletions(-) diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn index 6752a98a..a933fcd9 100644 --- a/openpower/isa/simplev.mdwn +++ b/openpower/isa/simplev.mdwn @@ -28,30 +28,32 @@ Pseudo-code: if (vf & (¬vs) & ¬(ms)) = 1 then step <- SVSTATE_NEXT(SVi, 0b0) - if _RT != 0b00000 then + if _RT != 0 then GPR(_RT) <- [0]*57 || step else VLimm <- SVi + 1 - if vs = 1 then - if _RA != 0 then - VL <- (RA|0)[57:63] - else - VL <- VLimm[0:6] - else + if vs = 0 then VL <- SVSTATE[7:13] + else if _RA != 0 then + VL <- (RA)[57:63] + else if _RT != 0 then + VL <- CTR + else + VL <- VLimm[0:6] if ms = 1 then MVL <- VLimm[0:6] else MVL <- SVSTATE[0:6] - if VL > MVL then - VL = MVL + if VL >u MVL then + VL <- MVL SVSTATE[0:6] <- MVL SVSTATE[7:13] <- VL - if _RT != 0b00000 then + if _RT != 0 then GPR(_RT) <- [0]*57 || VL - # set requested Vertical-First mode, clear persist - SVSTATE[63] <- vf - SVSTATE[62] <- 0b0 + if ((¬vs) & ¬(ms)) = 0 then + # set requested Vertical-First mode, clear persist + SVSTATE[63] <- vf + SVSTATE[62] <- 0b0 Special Registers Altered: diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py index ec86b198..11605740 100644 --- a/src/openpower/decoder/isa/test_caller_setvl.py +++ b/src/openpower/decoder/isa/test_caller_setvl.py @@ -132,7 +132,7 @@ class DecoderTestCase(FHDLTestCase): def test_setvl_1(self): """straight setvl, testing if VL and MVL are over-ridden """ - lst = SVP64Asm(["setvl 1, 0, 10, 0, 1, 1", + lst = SVP64Asm(["setvl 0, 0, 10, 0, 1, 1", ]) lst = list(lst) @@ -149,9 +149,31 @@ class DecoderTestCase(FHDLTestCase): print (" mvl", bin(sim.svstate.maxvl)) self.assertEqual(sim.svstate.vl, 10) self.assertEqual(sim.svstate.maxvl, 10) - self.assertEqual(sim.svstate.maxvl, 10) print(" gpr1", sim.gpr(1)) - self.assertEqual(sim.gpr(1), SelectableInt(10, 64)) + self.assertEqual(sim.gpr(1), SelectableInt(0, 64)) + + def test_setvl_2(self): + """setvl, testing if VL is transferred to RT, and MVL truncates it + """ + lst = SVP64Asm(["setvl 1, 0, 2, 0, 0, 1", + ]) + lst = list(lst) + + # SVSTATE (in this case, VL=2), want to see if these get changed + svstate = SVP64State() + svstate.vl = 10 # VL + svstate.maxvl = 10 # MAXVL + print ("SVSTATE", bin(svstate.asint())) + + with Program(lst, bigendian=False) as program: + sim = self.run_tst_program(program, svstate=svstate) + print ("SVSTATE after", bin(sim.svstate.asint())) + print (" vl", bin(sim.svstate.vl)) + print (" mvl", bin(sim.svstate.maxvl)) + self.assertEqual(sim.svstate.maxvl, 2) + self.assertEqual(sim.svstate.vl, 2) + print(" gpr1", sim.gpr(1)) + self.assertEqual(sim.gpr(1), SelectableInt(2, 64)) def test_svstep_inner_loop_6(self): """tests svstep inner loop, running 6 times, looking for "k". @@ -380,8 +402,9 @@ class DecoderTestCase(FHDLTestCase): * 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 * 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 """ - isa = SVP64Asm(["setvl 3, 0, 2, 0, 1, 1", - 'sv.add 1.v, 5.v, 9.v' + isa = SVP64Asm(["setvl 0, 0, 2, 0, 1, 1", + 'sv.add 1.v, 5.v, 9.v', + "setvl 3, 0, 0, 0, 0, 0", ]) lst = list(isa) print ("listing", lst) @@ -405,27 +428,28 @@ class DecoderTestCase(FHDLTestCase): def test_svstep_add_1(self): """tests svstep with an add, when it reaches VL - lst = SVP64Asm(["setvl 3, 0, 2, 1, 1, 1", + lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1", 'sv.add 1.v, 5.v, 9.v', "setvl. 0, 0, 1, 1, 0, 0", 'sv.add 1.v, 5.v, 9.v', - "setvl. 0, 0, 1, 1, 0, 0" + "setvl. 3, 0, 1, 1, 0, 0" ]) sequence is as follows: * setvl sets VL=2 but also "Vertical First" mode. - this sets MSR[SVF]. + this sets SVSTATE[SVF]. * first add, which has srcstep/dststep = 0, does add 1,5,9 * svstep EXPLICITLY walks srcstep/dststep to next element * second add, which now has srcstep/dststep = 1, does add 2,6,10 * svstep EXPLICITLY walks srcstep/dststep to next element, which now equals VL. srcstep and dststep are both set to - zero, and MSR[SVF] is cleared. + zero """ - lst = SVP64Asm(["setvl 3, 0, 2, 1, 1, 1", + lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1", 'sv.add 1.v, 5.v, 9.v', "setvl. 0, 0, 1, 1, 0, 0", # svstep 'sv.add 1.v, 5.v, 9.v', - "setvl. 0, 0, 1, 1, 0, 0" # svstep + "setvl. 3, 0, 1, 1, 0, 0", # svstep + "setvl 4, 0, 0, 0, 0, 0" # svstep ]) lst = list(lst) @@ -446,7 +470,7 @@ class DecoderTestCase(FHDLTestCase): expected_regs = deepcopy(initial_regs) expected_regs[1] = 0x5555 expected_regs[2] = 0x3334 - expected_regs[3] = 2 # setvl places copy of VL here + expected_regs[4] = 2 # setvl places copy of VL here with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) @@ -474,7 +498,7 @@ class DecoderTestCase(FHDLTestCase): def test_svstep_add_2(self): """tests svstep with a branch. - lst = SVP64Asm(["setvl 3, 0, 2, 1, 1, 1", + lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1", 'sv.add 1.v, 5.v, 9.v', "setvl. 0, 0, 1, 1, 0, 0", "bc 6, 3, -0xc" @@ -500,7 +524,7 @@ class DecoderTestCase(FHDLTestCase): first, then looping back and running all element 1, then all element 2 etc. """ - lst = SVP64Asm(["setvl 3, 0, 2, 1, 1, 1", + lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1", 'sv.add 1.v, 5.v, 9.v', "setvl. 0, 0, 1, 1, 0, 0", # svstep - this is 64-bit! "bc 6, 3, -0xc" # branch to add (64-bit op so -0xc!) @@ -524,7 +548,6 @@ class DecoderTestCase(FHDLTestCase): expected_regs = deepcopy(initial_regs) expected_regs[1] = 0x5555 expected_regs[2] = 0x3334 - expected_regs[3] = 2 # setvl places copy of VL here with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) @@ -579,7 +602,7 @@ class DecoderTestCase(FHDLTestCase): def test_svstep_iota(self): """tests svstep "straight", placing srcstep, dststep into vector """ - lst = SVP64Asm(["setvl 1, 0, 4, 0, 1, 1", + lst = SVP64Asm(["setvl 0, 0, 4, 0, 1, 1", "sv.svstep 0.v, 5, 1", # svstep get vector srcstep "sv.svstep. 4.v, 6, 1", # svstep get vector dststep ]) diff --git a/src/openpower/decoder/isa/test_caller_svstate.py b/src/openpower/decoder/isa/test_caller_svstate.py index 5a0490c0..e228b8ce 100644 --- a/src/openpower/decoder/isa/test_caller_svstate.py +++ b/src/openpower/decoder/isa/test_caller_svstate.py @@ -65,7 +65,7 @@ class SVSTATETestCase(FHDLTestCase): def test_svstep_add_1(self): """tests svstep with an add, using scalar adds, when it reaches VL - lst = SVP64Asm(["setvl 3, 0, 2, 1, 1, 1", + lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1", 'sv.add 1, 5.v, 9.v', 'sv.addi 12.v, 1, 1', "setvl. 0, 0, 1, 1, 0, 0", @@ -77,7 +77,7 @@ class SVSTATETestCase(FHDLTestCase): sequence is as follows: * setvl sets VL=2 but also "Vertical First" mode. - this sets MSR[SVF]. + this sets SVSTATE[SVF]. * first add, which has srcstep/dststep = 0, does add 1,5,9 * first addi, which has srcstep/dststep = 0, does addi 12, 1, #1 * svstep EXPLICITLY walks srcstep/dststep to next element @@ -86,7 +86,7 @@ class SVSTATETestCase(FHDLTestCase): * second addi, which has srcstep/dststep = 1, does addi 13, 1, #1 * svstep EXPLICITLY walks srcstep/dststep to next element, which now equals VL. srcstep and dststep are both set to - zero, and MSR[SVF] is cleared. CR0.SO is set to 1 because + zero. CR0.SO is set to 1 because it is the end of the looping. the first add will write 0x5555 into r1, then the vector-addi @@ -97,7 +97,7 @@ class SVSTATETestCase(FHDLTestCase): store the result in r13 (0x3335). """ - lst = SVP64Asm(["setvl 3, 0, 2, 1, 1, 1", + lst = SVP64Asm(["setvl 0, 0, 2, 1, 1, 1", 'sv.add 1, 5.v, 9.v', # scalar dest (into r1) 'sv.addi 12.v, 1, 1', # scalar src (from r1) "setvl. 0, 0, 1, 1, 0, 0", # svstep @@ -125,7 +125,6 @@ class SVSTATETestCase(FHDLTestCase): expected_regs[1] = 0x3334 # last temporary expected_regs[12] = 0x5556 expected_regs[13] = 0x3335 - expected_regs[3] = 2 # setvl places copy of VL here with Program(lst, bigendian=False) as program: sim = self.run_tst_program(program, initial_regs, svstate=svstate) -- 2.30.2