From 6d2d70d8796eecd7a8c0fea0c42f64303a74ba7a Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 29 Sep 2015 13:12:27 +0800
Subject: [PATCH] fhdl/FullMemoryWE: fix clocking

---
 migen/fhdl/simplify.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/migen/fhdl/simplify.py b/migen/fhdl/simplify.py
index 6d91fd0e..dba41beb 100644
--- a/migen/fhdl/simplify.py
+++ b/migen/fhdl/simplify.py
@@ -41,7 +41,7 @@ class FullMemoryWE(ModuleTransformer):
                             re=port.re,
                             we_granularity=0,
                             mode=port.mode,
-                            clock_domain=port.clock)
+                            clock_domain=port.clock.cd)
                         newmem.ports.append(newport)
                         newspecials.add(newport)
                 self.replacments[orig] = newmems
-- 
2.30.2