From 6d37f2877ef27dcec1eb1d39e7f06b3e2386bcb8 Mon Sep 17 00:00:00 2001 From: Adrian Herrera Date: Thu, 12 Dec 2019 16:25:46 +0000 Subject: [PATCH] dev-arm: GICv3, handle GICR_ICFGR0 WI behaviour Architecture states write accesses to GICR_ICFGR0 are WI. This patch implements handling of this behaviour instead of crashing as an invalid offset. This is required to support certain software behaviour. Change-Id: I1f8c57838566c360d243a925306ec35c64a920b2 Reviewed-by: Giacomo Travaglini Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24063 Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/dev/arm/gic_v3_redistributor.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/dev/arm/gic_v3_redistributor.cc b/src/dev/arm/gic_v3_redistributor.cc index 75fd9b326..f071c5bc7 100644 --- a/src/dev/arm/gic_v3_redistributor.cc +++ b/src/dev/arm/gic_v3_redistributor.cc @@ -579,6 +579,9 @@ Gicv3Redistributor::write(Addr addr, uint64_t data, size_t size, break; + case GICR_ICFGR0: // SGI Configuration Register + // WI + return; case GICR_ICFGR1: { // PPI Configuration Register int first_intid = Gicv3::SGI_MAX; -- 2.30.2