From 6d53d069929c92b2e46da466a3bdd7894921a060 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Sat, 13 Aug 2016 15:09:31 +0800 Subject: [PATCH] sim: v850: invert sim_cpu storage --- sim/v850/interp.c | 15 +++++++++------ sim/v850/sim-main.h | 24 ++++++++++++------------ sim/v850/v850.igen | 4 ++-- 3 files changed, 23 insertions(+), 20 deletions(-) diff --git a/sim/v850/interp.c b/sim/v850/interp.c index ab98571395b..4fa900eef2b 100644 --- a/sim/v850/interp.c +++ b/sim/v850/interp.c @@ -50,6 +50,8 @@ const char *interrupt_names[] = static void do_interrupt (SIM_DESC sd, void *data) { + sim_cpu *cpu = STATE_CPU (sd, 0); + struct v850_sim_cpu *v850_cpu = V850_SIM_CPU (cpu); const char **interrupt_name = (const char**)data; enum interrupt_type inttype; inttype = (interrupt_name - STATE_WATCHPOINTS (sd)->interrupt_names); @@ -74,9 +76,9 @@ do_interrupt (SIM_DESC sd, void *data) ignores subsequent NMIs, so we don't need to count them. Just keep re-scheduling a single NMI until it manages to be delivered */ - if (STATE_CPU (sd, 0)->pending_nmi != NULL) - sim_events_deschedule (sd, STATE_CPU (sd, 0)->pending_nmi); - STATE_CPU (sd, 0)->pending_nmi = + if (v850_cpu->pending_nmi != NULL) + sim_events_deschedule (sd, v850_cpu->pending_nmi); + v850_cpu->pending_nmi = sim_events_schedule (sd, 1, do_interrupt, data); return; } @@ -204,7 +206,8 @@ sim_open (SIM_OPEN_KIND kind, cb->syscall_map = cb_v850_syscall_map; /* The cpu data is kept in a separately allocated chunk of memory. */ - if (sim_cpu_alloc_all (sd, 1) != SIM_RC_OK) + if (sim_cpu_alloc_all_extra (sd, 1, sizeof (struct v850_sim_cpu)) + != SIM_RC_OK) return 0; /* for compatibility */ @@ -281,8 +284,8 @@ sim_open (SIM_OPEN_KIND kind, case bfd_mach_v850e2: case bfd_mach_v850e2v3: case bfd_mach_v850e3v5: - STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT - | PSW_CY | PSW_OV | PSW_S | PSW_Z); + V850_SIM_CPU (STATE_CPU (sd, 0))->psw_mask = + (PSW_NP | PSW_EP | PSW_ID | PSW_SAT | PSW_CY | PSW_OV | PSW_S | PSW_Z); break; } diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h index ab7e47aa240..970a1486ea1 100644 --- a/sim/v850/sim-main.h +++ b/sim/v850/sim-main.h @@ -1,6 +1,8 @@ #ifndef SIM_MAIN_H #define SIM_MAIN_H +#define SIM_HAVE_COMMON_SIM_CPU + /* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */ #define WITH_TARGET_WORD_MSB 31 @@ -32,16 +34,14 @@ typedef struct _v850_regs { reg64_t vregs[32]; /* vector registers. */ } v850_regs; -struct _sim_cpu -{ - /* ... simulator specific members ... */ +struct v850_sim_cpu { v850_regs reg; reg_t psw_mask; /* only allow non-reserved bits to be set */ sim_event *pending_nmi; - /* ... base type ... */ - sim_cpu_base base; }; +#define V850_SIM_CPU(cpu) ((struct v850_sim_cpu *) CPU_ARCH_DATA (cpu)) + /* For compatibility, until all functions converted to passing SIM_DESC as an argument */ extern SIM_DESC simulator; @@ -90,15 +90,15 @@ nia = PC /* new */ -#define GR ((CPU)->reg.regs) -#define SR ((CPU)->reg.sregs) -#define VR ((CPU)->reg.vregs) -#define MPU0_SR ((STATE_CPU (sd, 0))->reg.mpu0_sregs) -#define MPU1_SR ((STATE_CPU (sd, 0))->reg.mpu1_sregs) -#define FPU_SR ((STATE_CPU (sd, 0))->reg.fpu_sregs) +#define GR (V850_SIM_CPU (CPU)->reg.regs) +#define SR (V850_SIM_CPU (CPU)->reg.sregs) +#define VR (V850_SIM_CPU (CPU)->reg.vregs) +#define MPU0_SR (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.mpu0_sregs) +#define MPU1_SR (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.mpu1_sregs) +#define FPU_SR (V850_SIM_CPU (STATE_CPU (sd, 0))->reg.fpu_sregs) /* old */ -#define State (STATE_CPU (simulator, 0)->reg) +#define State (V850_SIM_CPU (STATE_CPU (simulator, 0))->reg) #define PC (State.pc) #define SP_REGNO 3 #define SP (State.regs[SP_REGNO]) diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen index eb32c0f5ec3..6bfabc08ea0 100644 --- a/sim/v850/v850.igen +++ b/sim/v850/v850.igen @@ -370,7 +370,7 @@ rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1 "ctret" { nia = (CTPC & ~1); - PSW = (CTPSW & (CPU)->psw_mask); + PSW = (CTPSW & V850_SIM_CPU (CPU)->psw_mask); TRACE_BRANCH1 (PSW); } @@ -954,7 +954,7 @@ regID,111111,RRRRR + selID,00000100000:IX:::ldsr /* FIXME: For now we ignore the selID. */ if (idecode_issue == idecode_v850e3v5_issue && selID != 0) { - (CPU)->reg.selID_sregs[selID][regID] = sreg; + V850_SIM_CPU (CPU)->reg.selID_sregs[selID][regID] = sreg; } else if (( idecode_issue == idecode_v850e2_issue || idecode_issue == idecode_v850e3v5_issue -- 2.30.2