From 6d77ed4073220e75fc10b99daebc6e0946190c02 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 18 Apr 2021 21:27:30 +0100 Subject: [PATCH] create signal on test_issuer which gives PLL clk_sel_i a useful name --- src/soc/clock/dummypll.py | 4 ---- src/soc/simple/issuer.py | 6 +++++- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/soc/clock/dummypll.py b/src/soc/clock/dummypll.py index 168822c8..912490d2 100644 --- a/src/soc/clock/dummypll.py +++ b/src/soc/clock/dummypll.py @@ -9,7 +9,6 @@ class DummyPLL(Elaboratable): self.clk_24_i = Signal(name="ref", reset_less=True) # external incoming self.sel_a0_i = Signal(name="a0", reset_less=True) # PLL selection self.sel_a1_i = Signal(name="a1", reset_less=True) # PLL selection - self.clk_sel_i = Signal(2, reset_less=True) # same as a0,a1 self.clk_pll_o = Signal(name="out", reset_less=True) # output clock self.pll_18_o = Signal(name="div_out_test", reset_less=True) # test out self.pll_ana_o = Signal(name="vco_test_ana", reset_less=True) # analog @@ -22,9 +21,6 @@ class DummyPLL(Elaboratable): m.d.comb += self.pll_ana_o.eq(self.clk_24_i) m.d.comb += self.pll_18_o.eq(~self.clk_24_i) - # same API - m.d.comb += self.clk_sel_i.eq(Cat(self.sel_a0_i, self.sel_a1_i)) - #self.attrs['blackbox'] = 1 return m diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 725823da..a5f7304f 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -1155,6 +1155,7 @@ class TestIssuer(Elaboratable): self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll if self.pll_en: self.pll_18_o = Signal(reset_less=True) + self.clk_sel_i = Signal(reset_less=True) def elaborate(self, platform): m = Module() @@ -1183,6 +1184,9 @@ class TestIssuer(Elaboratable): # output 18 mhz PLL test signal comb += self.pll_18_o.eq(pll.pll_18_o) + # input to pll clock selection + comb += Cat(pll.sel_a0_i, pll.sel_a1_i).eq(self.clk_sel_i) + # now wire up ResetSignals. don't mind them being in this domain pll_rst = ResetSignal("pllclk") comb += pll_rst.eq(ResetSignal()) @@ -1206,7 +1210,7 @@ class TestIssuer(Elaboratable): ports.append(ClockSignal()) ports.append(ResetSignal()) if self.pll_en: - ports.append(self.pll.clk_sel_i) + ports.append(self.clk_sel_i) ports.append(self.pll_18_o) ports.append(self.pll.pll_ana_o) return ports -- 2.30.2