From 6d7e169ebd50ff5c2ba8f251877ed5a2fb489a2d Mon Sep 17 00:00:00 2001 From: Jan Hubicka Date: Thu, 2 Nov 2017 14:49:31 +0100 Subject: [PATCH] * x86-tune.def (X86_TUNE_USE_INCDEC): Enable for Haswell+. From-SVN: r254343 --- gcc/ChangeLog | 4 ++++ gcc/config/i386/x86-tune.def | 11 ++++++++--- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cb46f71ce77..067164afb71 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2017-11-02 Jan Hubicka + + * x86-tune.def (X86_TUNE_USE_INCDEC): Enable for Haswell+. + 2017-11-02 Richard Biener PR tree-optimization/82795 diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index c7099d7d78b..99282c88341 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -220,10 +220,15 @@ DEF_TUNE (X86_TUNE_LCP_STALL, "lcp_stall", m_CORE_ALL | m_GENERIC) as "add mem, reg". */ DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_LAKEMONT | m_PPRO)) -/* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions. */ +/* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions. + + Core2 and nehalem has stall of 7 cycles for partial flag register stalls. + Sandy bridge and Ivy bridge generate extra uop. On Haswell this extra uop + is output only when the values needs to be really merged, which is not + done by GCC generated code. */ DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec", - ~(m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL - | m_KNL | m_KNM | m_GENERIC)) + ~(m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE + | m_BONNELL | m_SILVERMONT | m_INTEL | m_KNL | m_KNM | m_GENERIC)) /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred for DFmode copies */ -- 2.30.2