From 6d861c6e57ffcaf715b47df1286516e00587699e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 11 Mar 2020 10:38:28 +0100 Subject: [PATCH] cores/pwm: add CSR descriptions. --- litex/soc/cores/pwm.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/litex/soc/cores/pwm.py b/litex/soc/cores/pwm.py index f3167de8..3adc0ca2 100644 --- a/litex/soc/cores/pwm.py +++ b/litex/soc/cores/pwm.py @@ -49,9 +49,13 @@ class PWM(Module, AutoCSR): self.add_csr(clock_domain) def add_csr(self, clock_domain): - self._enable = CSRStorage() - self._width = CSRStorage(32) - self._period = CSRStorage(32) + self._enable = CSRStorage(description="""PWM Enable.\n + Write ``1`` to enable PWM.""") + self._width = CSRStorage(32, description="""PWM Width.\n + Defines the *Duty cycle* of the PWM. PWM is active high for *Width* ``{cd}_clk`` cycles and + active low for *Period - Width* ``{cd}_clk`` cycles.""".format(cd=clock_domain)) + self._period = CSRStorage(32, description="""PWM Period.\n + Defines the *Period* of the PWM in ``{cd}_clk`` cycles.""".format(cd=clock_domain)) n = 0 if clock_domain == "sys" else 2 self.specials += [ -- 2.30.2