From 6d8bfa2c00696fd9b6c93a2dbabf98197af00df9 Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Mon, 23 Oct 2023 09:17:55 +0300 Subject: [PATCH] test_syscall: hardcode MSR validation --- src/openpower/decoder/isa/test_syscall.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/openpower/decoder/isa/test_syscall.py b/src/openpower/decoder/isa/test_syscall.py index c36dc781..6c782409 100644 --- a/src/openpower/decoder/isa/test_syscall.py +++ b/src/openpower/decoder/isa/test_syscall.py @@ -63,7 +63,12 @@ class SyscallTestCase(FHDLTestCase): self.assertEqual(sim.spr['SRR0'], 8) # PC to return to: CIA+4 self.assertEqual(sim.spr['SRR1'], SRR1) # MSR to restore after sc return + + # FIXME this is currently hardcoded to the same way as in test_trap.py. + # However, I'd have expected 0x9000000000002903, not 0x9000000000000001. + MSR = SelectableInt(0x9000000000000001, 64) self.assertEqual(sim.msr, MSR) # MSR changed to this by sc/trap + print("SYSCALL SRR1", hex(int(SRR1)), hex(int(sim.spr['SRR1']))) print("SYSCALL MSR", hex(int(MSR)), hex(int(sim.msr)), hex(DEFAULT_MSR)) return sim -- 2.30.2