From 6dd0b514acce675c627bd502189ab4cd3153f78a Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 17 Oct 2019 10:21:41 +1100 Subject: [PATCH] Reduce wishbone address size to 32-bit For now ... it reduces the routing pressure on the FPGA This needs manual adjustment of the address decoder in soc.vhdl, at least until I can figure out how to deal with std_match Signed-off-by: Benjamin Herrenschmidt # Conflicts: # soc.vhdl # Conflicts: # soc.vhdl --- soc.vhdl | 6 +++--- wishbone_types.vhdl | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/soc.vhdl b/soc.vhdl index 94ab393..458a751 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -111,11 +111,11 @@ begin SLAVE_NONE); variable slave : slave_type; begin - -- Simple address decoder + -- Simple address decoder. slave := SLAVE_NONE; - if wb_master_out.adr(63 downto 24) = x"0000000000" then + if wb_master_out.adr(31 downto 24) = x"00" then slave := SLAVE_MEMORY; - elsif wb_master_out.adr(63 downto 24) = x"00000000c0" then + elsif wb_master_out.adr(31 downto 24) = x"c0" then if wb_master_out.adr(23 downto 12) = x"002" then slave := SLAVE_UART_0; end if; diff --git a/wishbone_types.vhdl b/wishbone_types.vhdl index 9284244..12f0bc7 100644 --- a/wishbone_types.vhdl +++ b/wishbone_types.vhdl @@ -2,7 +2,7 @@ library ieee; use ieee.std_logic_1164.all; package wishbone_types is - constant wishbone_addr_bits : integer := 64; + constant wishbone_addr_bits : integer := 32; constant wishbone_data_bits : integer := 64; constant wishbone_sel_bits : integer := wishbone_data_bits/8; -- 2.30.2