From 6dd74463ea50706652a42ac993ac3a2e22b86b58 Mon Sep 17 00:00:00 2001 From: Prachi Godbole Date: Wed, 22 Jul 2015 12:46:09 +0000 Subject: [PATCH] Add scheduling for M51xx core family. gcc/ * config/mips/m5100.md: New file. * config/mips/mips-cpus.def (m5100, m5101): Define. * config/mips/mips-tables.opt: Regenerate. * config/mips/mips.c (mips_rtx_cost_data): Add costs for m5100. * config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Map -march=m5100 and -march=m5101 to -mips32r5. (MIPS_ARCH_FLOAT_SPEC): Map -m5101 to -msoft-float. (MIPS_ISA_NAN2008_SPEC): Map -march=m51* to -mnan=2008 if !-msoft-float. * config/mips/mips.md: Include m5100.md. (processor): Add m5100. * doc/invoke.texi (-march=@var{arch}): Add m5100, m5101. From-SVN: r226066 --- gcc/ChangeLog | 15 +++ gcc/config/mips/m5100.md | 220 ++++++++++++++++++++++++++++++++ gcc/config/mips/mips-cpus.def | 2 + gcc/config/mips/mips-tables.opt | 40 +++--- gcc/config/mips/mips.c | 13 ++ gcc/config/mips/mips.h | 7 +- gcc/config/mips/mips.md | 2 + gcc/doc/invoke.texi | 1 + 8 files changed, 280 insertions(+), 20 deletions(-) create mode 100644 gcc/config/mips/m5100.md diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e0106d3350b..e6b8485f4d4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,18 @@ +2015-07-22 Prachi Godbole + + * config/mips/m5100.md: New file. + * config/mips/mips-cpus.def (m5100, m5101): Define. + * config/mips/mips-tables.opt: Regenerate. + * config/mips/mips.c (mips_rtx_cost_data): Add costs for m5100. + * config/mips/mips.h (MIPS_ISA_LEVEL_SPEC): Map -march=m5100 and + -march=m5101 to -mips32r5. + (MIPS_ARCH_FLOAT_SPEC): Map -m5101 to -msoft-float. + (MIPS_ISA_NAN2008_SPEC): Map -march=m51* to -mnan=2008 if + !-msoft-float. + * config/mips/mips.md: Include m5100.md. + (processor): Add m5100. + * doc/invoke.texi (-march=@var{arch}): Add m5100, m5101. + 2015-07-22 Robert Suchanek * config/mips/mips-cpus.def (interaptiv): Define. diff --git a/gcc/config/mips/m5100.md b/gcc/config/mips/m5100.md new file mode 100644 index 00000000000..f860eb211f8 --- /dev/null +++ b/gcc/config/mips/m5100.md @@ -0,0 +1,220 @@ +;; DFA-based pipeline description for MIPS32 models M5100. +;; +;; Copyright (C) 2015 Free Software Foundation, Inc. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_automaton "m51_alu_pipe, m51_mdu_pipe, m51_fpu_pipe") +(define_cpu_unit "m51_mul" "m51_mdu_pipe") +(define_cpu_unit "m51_alu" "m51_alu_pipe") +(define_cpu_unit "m51_fpu" "m51_fpu_pipe") + +;; -------------------------------------------------------------- +;; ALU Instructions +;; -------------------------------------------------------------- + +;; ALU: Logicals +(define_insn_reservation "m51_int_logical" 1 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "logical,move,signext,slt")) + "m51_alu") + +;; Arithmetics +(define_insn_reservation "m51_int" 1 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "arith,const,shift,clz")) + "m51_alu") + +(define_insn_reservation "m51_int_nop" 0 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "nop")) + "nothing") + +;; Conditional move +(define_insn_reservation "m51_int_cmove" 1 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "condmove") + (eq_attr "mode" "SI,DI"))) + "m51_alu") + +;; Call +(define_insn_reservation "m51_int_call" 1 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "call")) + "m51_alu") + +;; branch/jump +(define_insn_reservation "m51_int_jump" 1 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "branch,jump")) + "m51_alu") + +;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs +;; prefetch: prefetch, prefetchx +(define_insn_reservation "m51_int_load" 3 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "load,prefetch,prefetchx")) + "m51_alu") + +;; stores +(define_insn_reservation "m51_int_store" 1 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "store")) + "m51_alu") + +;; -------------------------------------------------------------- +;; MDU Instructions +;; -------------------------------------------------------------- + +;; High performance fully pipelined multiplier +;; MULT to HI/LO +(define_insn_reservation "m51_int_mult" 2 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "imul,imadd")) + "m51_alu+m51_mul*2") + +;; MUL to GPR +(define_insn_reservation "m51_int_mul3" 2 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "imul3")) + "(m51_alu*2)+(m51_mul*2)") + +;; mfhi, mflo +(define_insn_reservation "m51_int_mfhilo" 1 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "mfhi,mflo")) + "m51_mul") + +;; mthi, mtlo +(define_insn_reservation "m51_int_mthilo" 1 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "mthi,mtlo")) + "m51_mul") + +;; div +(define_insn_reservation "m51_int_div_si" 34 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "idiv")) + "m51_alu+m51_mul*34") + +;; -------------------------------------------------------------- +;; Floating Point Instructions +;; -------------------------------------------------------------- + +;; fadd, fabs, fneg +(define_insn_reservation "m51_fadd" 4 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "fadd,fabs,fneg")) + "m51_fpu") + +;; fmove +(define_insn_reservation "m51_fmove" 4 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "fmove")) + "m51_fpu") + +;; conditional move +(define_insn_reservation "m51_fp_cmove" 4 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "condmove") + (eq_attr "mode" "SF,DF"))) + "m51_fpu") + +;; fload +(define_insn_reservation "m51_fload" 3 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "fpload,fpidxload")) + "m51_fpu") + +;; fstore +(define_insn_reservation "m51_fstore" 1 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "fpstore,fpidxstore")) + "m51_fpu") + +;; fmul, fmadd +(define_insn_reservation "m51_fmul_sf" 4 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "fmul,fmadd") + (eq_attr "mode" "SF"))) + "m51_fpu") + +(define_insn_reservation "m51_fmul_df" 5 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "fmul,fmadd") + (eq_attr "mode" "DF"))) + "m51_fpu*2") + +;; fdiv, fsqrt +(define_insn_reservation "m51_fdiv_sf" 17 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "fdiv,fsqrt") + (eq_attr "mode" "SF"))) + "m51_fpu*14") + +(define_insn_reservation "m51_fdiv_df" 32 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "fdiv,fsqrt") + (eq_attr "mode" "DF"))) + "m51_fpu*29") + +;; frsqrt +(define_insn_reservation "m51_frsqrt_sf" 17 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "frsqrt") + (eq_attr "mode" "SF"))) + "m51_fpu*14") + +(define_insn_reservation "m51_frsqrt_df" 35 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "frsqrt") + (eq_attr "mode" "DF"))) + "m51_fpu*31") + +;; fcmp +(define_insn_reservation "m51_fcmp" 4 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "fcmp")) + "m51_fpu") + +;; fcvt +;; cvt.s.d +(define_insn_reservation "m51_fcvt_6" 6 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "fcvt") + (eq_attr "cnv_mode" "D2S"))) + "m51_fpu") + +;; trunc +(define_insn_reservation "m51_fcvt_5" 5 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "fcvt") + (eq_attr "cnv_mode" "D2I,S2I"))) + "m51_fpu") + +;; cvt +(define_insn_reservation "m51_fcvt_4" 4 + (and (eq_attr "cpu" "m5100") + (and (eq_attr "type" "fcvt") + (eq_attr "cnv_mode" "S2D,I2D,I2S"))) + "m51_fpu") + +;; mtc, mfc +(define_insn_reservation "m51_move_to_from_c1" 2 + (and (eq_attr "cpu" "m5100") + (eq_attr "type" "mtc, mfc")) + "m51_fpu") diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index 63a0d6e9251..55c0cf6b3f7 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -151,6 +151,8 @@ MIPS_CPU ("interaptiv", PROCESSOR_24KF2_1, 33, 0) /* MIPS32 Release 5 processors. */ MIPS_CPU ("p5600", PROCESSOR_P5600, 36, PTF_AVOID_BRANCHLIKELY) +MIPS_CPU ("m5100", PROCESSOR_M5100, 36, PTF_AVOID_BRANCHLIKELY) +MIPS_CPU ("m5101", PROCESSOR_M5100, 36, PTF_AVOID_BRANCHLIKELY) /* MIPS64 processors. */ MIPS_CPU ("5kc", PROCESSOR_5KC, 64, 0) diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt index 8c6c4b1111b..1f5daa41e94 100644 --- a/gcc/config/mips/mips-tables.opt +++ b/gcc/config/mips/mips-tables.opt @@ -637,53 +637,59 @@ EnumValue Enum(mips_arch_opt_value) String(p5600) Value(86) Canonical EnumValue -Enum(mips_arch_opt_value) String(5kc) Value(87) Canonical +Enum(mips_arch_opt_value) String(m5100) Value(87) Canonical EnumValue -Enum(mips_arch_opt_value) String(r5kc) Value(87) +Enum(mips_arch_opt_value) String(m5101) Value(88) Canonical EnumValue -Enum(mips_arch_opt_value) String(5kf) Value(88) Canonical +Enum(mips_arch_opt_value) String(5kc) Value(89) Canonical EnumValue -Enum(mips_arch_opt_value) String(r5kf) Value(88) +Enum(mips_arch_opt_value) String(r5kc) Value(89) EnumValue -Enum(mips_arch_opt_value) String(20kc) Value(89) Canonical +Enum(mips_arch_opt_value) String(5kf) Value(90) Canonical EnumValue -Enum(mips_arch_opt_value) String(r20kc) Value(89) +Enum(mips_arch_opt_value) String(r5kf) Value(90) EnumValue -Enum(mips_arch_opt_value) String(sb1) Value(90) Canonical +Enum(mips_arch_opt_value) String(20kc) Value(91) Canonical EnumValue -Enum(mips_arch_opt_value) String(sb1a) Value(91) Canonical +Enum(mips_arch_opt_value) String(r20kc) Value(91) EnumValue -Enum(mips_arch_opt_value) String(sr71000) Value(92) Canonical +Enum(mips_arch_opt_value) String(sb1) Value(92) Canonical EnumValue -Enum(mips_arch_opt_value) String(sr71k) Value(92) +Enum(mips_arch_opt_value) String(sb1a) Value(93) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlr) Value(93) Canonical +Enum(mips_arch_opt_value) String(sr71000) Value(94) Canonical EnumValue -Enum(mips_arch_opt_value) String(loongson3a) Value(94) Canonical +Enum(mips_arch_opt_value) String(sr71k) Value(94) EnumValue -Enum(mips_arch_opt_value) String(octeon) Value(95) Canonical +Enum(mips_arch_opt_value) String(xlr) Value(95) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon+) Value(96) Canonical +Enum(mips_arch_opt_value) String(loongson3a) Value(96) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon2) Value(97) Canonical +Enum(mips_arch_opt_value) String(octeon) Value(97) Canonical EnumValue -Enum(mips_arch_opt_value) String(octeon3) Value(98) Canonical +Enum(mips_arch_opt_value) String(octeon+) Value(98) Canonical EnumValue -Enum(mips_arch_opt_value) String(xlp) Value(99) Canonical +Enum(mips_arch_opt_value) String(octeon2) Value(99) Canonical + +EnumValue +Enum(mips_arch_opt_value) String(octeon3) Value(100) Canonical + +EnumValue +Enum(mips_arch_opt_value) String(xlp) Value(101) Canonical diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index c32532b0721..c3cd52d20b0 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -1280,6 +1280,19 @@ static const struct mips_rtx_cost_data COSTS_N_INSNS (41), /* int_div_di */ 1, /* branch_cost */ 4 /* memory_latency */ + }, + { /* M5100 */ + COSTS_N_INSNS (4), /* fp_add */ + COSTS_N_INSNS (4), /* fp_mult_sf */ + COSTS_N_INSNS (5), /* fp_mult_df */ + COSTS_N_INSNS (17), /* fp_div_sf */ + COSTS_N_INSNS (32), /* fp_div_df */ + COSTS_N_INSNS (5), /* int_mult_si */ + COSTS_N_INSNS (5), /* int_mult_di */ + COSTS_N_INSNS (34), /* int_div_si */ + COSTS_N_INSNS (68), /* int_div_di */ + 1, /* branch_cost */ + 4 /* memory_latency */ } }; diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 505e111b969..5bc562e9205 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -725,7 +725,7 @@ struct mips_cpu_info { |march=34k*|march=74k*|march=m14k*|march=1004k* \ |march=interaptiv: -mips32r2} \ %{march=mips32r3: -mips32r3} \ - %{march=mips32r5|march=p5600: -mips32r5} \ + %{march=mips32r5|march=p5600|march=m5100|march=m5101: -mips32r5} \ %{march=mips32r6: -mips32r6} \ %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ |march=xlr: -mips64} \ @@ -749,7 +749,7 @@ struct mips_cpu_info { "%{mhard-float|msoft-float|mno-float|march=mips*:; \ march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \ |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \ - |march=m14k*|march=octeon|march=xlr: -msoft-float; \ + |march=m14k*|march=m5101|march=octeon|march=xlr: -msoft-float; \ march=*: -mhard-float}" /* A spec condition that matches 32-bit options. It only works if @@ -772,7 +772,8 @@ struct mips_cpu_info { /* Infer a -mnan=2008 setting from a -mips argument. */ #define MIPS_ISA_NAN2008_SPEC \ - "%{mnan*:;mips32r6|mips64r6:-mnan=2008}" + "%{mnan*:;mips32r6|mips64r6:-mnan=2008;march=m51*: \ + %{!msoft-float:-mnan=2008}}" #if (MIPS_ABI_DEFAULT == ABI_O64 \ || MIPS_ABI_DEFAULT == ABI_N32 \ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index ad8ad9fff72..cde2b4eb979 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -69,6 +69,7 @@ p5600 w32 w64 + m5100 ]) (define_c_enum "unspec" [ @@ -1086,6 +1087,7 @@ "nothing") (include "p5600.md") +(include "m5100.md") (include "4k.md") (include "5k.md") (include "20kc.md") diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 7c7831efd57..413ac1666c8 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -17045,6 +17045,7 @@ The processor names are: @samp{loongson2e}, @samp{loongson2f}, @samp{loongson3a}, @samp{m4k}, @samp{m14k}, @samp{m14kc}, @samp{m14ke}, @samp{m14kec}, +@samp{m5100}, @samp{m5101}, @samp{octeon}, @samp{octeon+}, @samp{octeon2}, @samp{octeon3}, @samp{orion}, @samp{p5600}, -- 2.30.2