From 6df4618cac91499f411673b33a516a5310cfbf79 Mon Sep 17 00:00:00 2001 From: Srinath Parvathaneni Date: Tue, 17 Mar 2020 12:23:42 +0000 Subject: [PATCH] [ARM][GCC][3/1x]: MVE intrinsics with unary operand. This patch supports following MVE ACLE intrinsics with unary operand. vdupq_n_s8, vdupq_n_s16, vdupq_n_s32, vabsq_s8, vabsq_s16, vabsq_s32, vclsq_s8, vclsq_s16, vclsq_s32, vclzq_s8, vclzq_s16, vclzq_s32, vnegq_s8, vnegq_s16, vnegq_s32, vaddlvq_s32, vaddvq_s8, vaddvq_s16, vaddvq_s32, vmovlbq_s8, vmovlbq_s16, vmovltq_s8, vmovltq_s16, vmvnq_s8, vmvnq_s16, vmvnq_s32, vrev16q_s8, vrev32q_s8, vrev32q_s16, vqabsq_s8, vqabsq_s16, vqabsq_s32, vqnegq_s8, vqnegq_s16, vqnegq_s32, vcvtaq_s16_f16, vcvtaq_s32_f32, vcvtnq_s16_f16, vcvtnq_s32_f32, vcvtpq_s16_f16, vcvtpq_s32_f32, vcvtmq_s16_f16, vcvtmq_s32_f32, vmvnq_u8, vmvnq_u16, vmvnq_u32, vdupq_n_u8, vdupq_n_u16, vdupq_n_u32, vclzq_u8, vclzq_u16, vclzq_u32, vaddvq_u8, vaddvq_u16, vaddvq_u32, vrev32q_u8, vrev32q_u16, vmovltq_u8, vmovltq_u16, vmovlbq_u8, vmovlbq_u16, vrev16q_u8, vaddlvq_u32, vcvtpq_u16_f16, vcvtpq_u32_f32, vcvtnq_u16_f16, vcvtmq_u16_f16, vcvtmq_u32_f32, vcvtaq_u16_f16, vcvtaq_u32_f32, vdupq_n, vabsq, vclsq, vclzq, vnegq, vaddlvq, vaddvq, vmovlbq, vmovltq, vmvnq, vrev16q, vrev32q, vqabsq, vqnegq. A new register class "EVEN_REGS" which allows only even registers is added in this patch. The new constraint "e" allows only reigsters of EVEN_REGS class. Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more details. [1] https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * config/arm/arm.h (enum reg_class): Define new class EVEN_REGS. * config/arm/arm_mve.h (vdupq_n_s8): Define macro. (vdupq_n_s16): Likewise. (vdupq_n_s32): Likewise. (vabsq_s8): Likewise. (vabsq_s16): Likewise. (vabsq_s32): Likewise. (vclsq_s8): Likewise. (vclsq_s16): Likewise. (vclsq_s32): Likewise. (vclzq_s8): Likewise. (vclzq_s16): Likewise. (vclzq_s32): Likewise. (vnegq_s8): Likewise. (vnegq_s16): Likewise. (vnegq_s32): Likewise. (vaddlvq_s32): Likewise. (vaddvq_s8): Likewise. (vaddvq_s16): Likewise. (vaddvq_s32): Likewise. (vmovlbq_s8): Likewise. (vmovlbq_s16): Likewise. (vmovltq_s8): Likewise. (vmovltq_s16): Likewise. (vmvnq_s8): Likewise. (vmvnq_s16): Likewise. (vmvnq_s32): Likewise. (vrev16q_s8): Likewise. (vrev32q_s8): Likewise. (vrev32q_s16): Likewise. (vqabsq_s8): Likewise. (vqabsq_s16): Likewise. (vqabsq_s32): Likewise. (vqnegq_s8): Likewise. (vqnegq_s16): Likewise. (vqnegq_s32): Likewise. (vcvtaq_s16_f16): Likewise. (vcvtaq_s32_f32): Likewise. (vcvtnq_s16_f16): Likewise. (vcvtnq_s32_f32): Likewise. (vcvtpq_s16_f16): Likewise. (vcvtpq_s32_f32): Likewise. (vcvtmq_s16_f16): Likewise. (vcvtmq_s32_f32): Likewise. (vmvnq_u8): Likewise. (vmvnq_u16): Likewise. (vmvnq_u32): Likewise. (vdupq_n_u8): Likewise. (vdupq_n_u16): Likewise. (vdupq_n_u32): Likewise. (vclzq_u8): Likewise. (vclzq_u16): Likewise. (vclzq_u32): Likewise. (vaddvq_u8): Likewise. (vaddvq_u16): Likewise. (vaddvq_u32): Likewise. (vrev32q_u8): Likewise. (vrev32q_u16): Likewise. (vmovltq_u8): Likewise. (vmovltq_u16): Likewise. (vmovlbq_u8): Likewise. (vmovlbq_u16): Likewise. (vrev16q_u8): Likewise. (vaddlvq_u32): Likewise. (vcvtpq_u16_f16): Likewise. (vcvtpq_u32_f32): Likewise. (vcvtnq_u16_f16): Likewise. (vcvtmq_u16_f16): Likewise. (vcvtmq_u32_f32): Likewise. (vcvtaq_u16_f16): Likewise. (vcvtaq_u32_f32): Likewise. (__arm_vdupq_n_s8): Define intrinsic. (__arm_vdupq_n_s16): Likewise. (__arm_vdupq_n_s32): Likewise. (__arm_vabsq_s8): Likewise. (__arm_vabsq_s16): Likewise. (__arm_vabsq_s32): Likewise. (__arm_vclsq_s8): Likewise. (__arm_vclsq_s16): Likewise. (__arm_vclsq_s32): Likewise. (__arm_vclzq_s8): Likewise. (__arm_vclzq_s16): Likewise. (__arm_vclzq_s32): Likewise. (__arm_vnegq_s8): Likewise. (__arm_vnegq_s16): Likewise. (__arm_vnegq_s32): Likewise. (__arm_vaddlvq_s32): Likewise. (__arm_vaddvq_s8): Likewise. (__arm_vaddvq_s16): Likewise. (__arm_vaddvq_s32): Likewise. (__arm_vmovlbq_s8): Likewise. (__arm_vmovlbq_s16): Likewise. (__arm_vmovltq_s8): Likewise. (__arm_vmovltq_s16): Likewise. (__arm_vmvnq_s8): Likewise. (__arm_vmvnq_s16): Likewise. (__arm_vmvnq_s32): Likewise. (__arm_vrev16q_s8): Likewise. (__arm_vrev32q_s8): Likewise. (__arm_vrev32q_s16): Likewise. (__arm_vqabsq_s8): Likewise. (__arm_vqabsq_s16): Likewise. (__arm_vqabsq_s32): Likewise. (__arm_vqnegq_s8): Likewise. (__arm_vqnegq_s16): Likewise. (__arm_vqnegq_s32): Likewise. (__arm_vmvnq_u8): Likewise. (__arm_vmvnq_u16): Likewise. (__arm_vmvnq_u32): Likewise. (__arm_vdupq_n_u8): Likewise. (__arm_vdupq_n_u16): Likewise. (__arm_vdupq_n_u32): Likewise. (__arm_vclzq_u8): Likewise. (__arm_vclzq_u16): Likewise. (__arm_vclzq_u32): Likewise. (__arm_vaddvq_u8): Likewise. (__arm_vaddvq_u16): Likewise. (__arm_vaddvq_u32): Likewise. (__arm_vrev32q_u8): Likewise. (__arm_vrev32q_u16): Likewise. (__arm_vmovltq_u8): Likewise. (__arm_vmovltq_u16): Likewise. (__arm_vmovlbq_u8): Likewise. (__arm_vmovlbq_u16): Likewise. (__arm_vrev16q_u8): Likewise. (__arm_vaddlvq_u32): Likewise. (__arm_vcvtpq_u16_f16): Likewise. (__arm_vcvtpq_u32_f32): Likewise. (__arm_vcvtnq_u16_f16): Likewise. (__arm_vcvtmq_u16_f16): Likewise. (__arm_vcvtmq_u32_f32): Likewise. (__arm_vcvtaq_u16_f16): Likewise. (__arm_vcvtaq_u32_f32): Likewise. (__arm_vcvtaq_s16_f16): Likewise. (__arm_vcvtaq_s32_f32): Likewise. (__arm_vcvtnq_s16_f16): Likewise. (__arm_vcvtnq_s32_f32): Likewise. (__arm_vcvtpq_s16_f16): Likewise. (__arm_vcvtpq_s32_f32): Likewise. (__arm_vcvtmq_s16_f16): Likewise. (__arm_vcvtmq_s32_f32): Likewise. (vdupq_n): Define polymorphic variant. (vabsq): Likewise. (vclsq): Likewise. (vclzq): Likewise. (vnegq): Likewise. (vaddlvq): Likewise. (vaddvq): Likewise. (vmovlbq): Likewise. (vmovltq): Likewise. (vmvnq): Likewise. (vrev16q): Likewise. (vrev32q): Likewise. (vqabsq): Likewise. (vqnegq): Likewise. * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it. (UNOP_SNONE_NONE): Likewise. (UNOP_UNONE_UNONE): Likewise. (UNOP_UNONE_NONE): Likewise. * config/arm/constraints.md (e): Define new constriant to allow only even registers. * config/arm/mve.md (mve_vqabsq_s): Define RTL pattern. (mve_vnegq_s): Likewise. (mve_vmvnq_): Likewise. (mve_vdupq_n_): Likewise. (mve_vclzq_): Likewise. (mve_vclsq_s): Likewise. (mve_vaddvq_): Likewise. (mve_vabsq_s): Likewise. (mve_vrev32q_): Likewise. (mve_vmovltq_): Likewise. (mve_vmovlbq_): Likewise. (mve_vcvtpq_): Likewise. (mve_vcvtnq_): Likewise. (mve_vcvtmq_): Likewise. (mve_vcvtaq_): Likewise. (mve_vrev16q_v16qi): Likewise. (mve_vaddlvq_v4si): Likewise. gcc/testsuite/ChangeLog: 2020-03-17 Andre Vieira Mihail Ionescu Srinath Parvathaneni * gcc.target/arm/mve/intrinsics/vabsq_s16.c: New test. * gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddlvq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddlvq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vaddvq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vclsq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vclsq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vclsq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vclzq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovlbq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmovltq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmvnq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vnegq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqabsq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqabsq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqabsq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vqnegq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vqnegq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vqnegq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev16q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev16q_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vrev32q_u8.c: Likewise. --- gcc/ChangeLog | 183 +++++ gcc/config/arm/arm.h | 3 + gcc/config/arm/arm_mve.h | 740 ++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 31 + gcc/config/arm/constraints.md | 4 + gcc/config/arm/mve.md | 291 ++++++- gcc/testsuite/ChangeLog | 75 ++ .../gcc.target/arm/mve/intrinsics/vabsq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_s8.c | 22 + .../arm/mve/intrinsics/vaddlvq_s32.c | 22 + .../arm/mve/intrinsics/vaddlvq_u32.c | 22 + .../arm/mve/intrinsics/vaddvq_s16.c | 22 + .../arm/mve/intrinsics/vaddvq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_s8.c | 22 + .../arm/mve/intrinsics/vaddvq_u16.c | 22 + .../arm/mve/intrinsics/vaddvq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclsq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vclzq_u8.c | 22 + .../arm/mve/intrinsics/vcvtaq_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtaq_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtaq_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtaq_u32_f32.c | 14 + .../arm/mve/intrinsics/vcvtmq_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtmq_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtmq_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtmq_u32_f32.c | 14 + .../arm/mve/intrinsics/vcvtnq_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtnq_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtnq_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtpq_s16_f16.c | 14 + .../arm/mve/intrinsics/vcvtpq_s32_f32.c | 14 + .../arm/mve/intrinsics/vcvtpq_u16_f16.c | 14 + .../arm/mve/intrinsics/vcvtpq_u32_f32.c | 14 + .../arm/mve/intrinsics/vdupq_n_s16.c | 14 + .../arm/mve/intrinsics/vdupq_n_s32.c | 14 + .../arm/mve/intrinsics/vdupq_n_s8.c | 14 + .../arm/mve/intrinsics/vdupq_n_u16.c | 14 + .../arm/mve/intrinsics/vdupq_n_u32.c | 14 + .../arm/mve/intrinsics/vdupq_n_u8.c | 14 + .../arm/mve/intrinsics/vmovlbq_s16.c | 22 + .../arm/mve/intrinsics/vmovlbq_s8.c | 22 + .../arm/mve/intrinsics/vmovlbq_u16.c | 22 + .../arm/mve/intrinsics/vmovlbq_u8.c | 22 + .../arm/mve/intrinsics/vmovltq_s16.c | 22 + .../arm/mve/intrinsics/vmovltq_s8.c | 22 + .../arm/mve/intrinsics/vmovltq_u16.c | 22 + .../arm/mve/intrinsics/vmovltq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vmvnq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vnegq_s8.c | 22 + .../arm/mve/intrinsics/vqabsq_s16.c | 22 + .../arm/mve/intrinsics/vqabsq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqabsq_s8.c | 22 + .../arm/mve/intrinsics/vqnegq_s16.c | 22 + .../arm/mve/intrinsics/vqnegq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vqnegq_s8.c | 22 + .../arm/mve/intrinsics/vrev16q_s8.c | 22 + .../arm/mve/intrinsics/vrev16q_u8.c | 22 + .../arm/mve/intrinsics/vrev32q_s16.c | 22 + .../arm/mve/intrinsics/vrev32q_s8.c | 22 + .../arm/mve/intrinsics/vrev32q_u16.c | 22 + .../arm/mve/intrinsics/vrev32q_u8.c | 22 + .../arm/mve/intrinsics/vrev64q_s16.c | 2 +- .../arm/mve/intrinsics/vrev64q_s32.c | 2 +- 79 files changed, 2695 insertions(+), 8 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 98fc289716d..8f7b261ca9d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,186 @@ +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + + * config/arm/arm.h (enum reg_class): Define new class EVEN_REGS. + * config/arm/arm_mve.h (vdupq_n_s8): Define macro. + (vdupq_n_s16): Likewise. + (vdupq_n_s32): Likewise. + (vabsq_s8): Likewise. + (vabsq_s16): Likewise. + (vabsq_s32): Likewise. + (vclsq_s8): Likewise. + (vclsq_s16): Likewise. + (vclsq_s32): Likewise. + (vclzq_s8): Likewise. + (vclzq_s16): Likewise. + (vclzq_s32): Likewise. + (vnegq_s8): Likewise. + (vnegq_s16): Likewise. + (vnegq_s32): Likewise. + (vaddlvq_s32): Likewise. + (vaddvq_s8): Likewise. + (vaddvq_s16): Likewise. + (vaddvq_s32): Likewise. + (vmovlbq_s8): Likewise. + (vmovlbq_s16): Likewise. + (vmovltq_s8): Likewise. + (vmovltq_s16): Likewise. + (vmvnq_s8): Likewise. + (vmvnq_s16): Likewise. + (vmvnq_s32): Likewise. + (vrev16q_s8): Likewise. + (vrev32q_s8): Likewise. + (vrev32q_s16): Likewise. + (vqabsq_s8): Likewise. + (vqabsq_s16): Likewise. + (vqabsq_s32): Likewise. + (vqnegq_s8): Likewise. + (vqnegq_s16): Likewise. + (vqnegq_s32): Likewise. + (vcvtaq_s16_f16): Likewise. + (vcvtaq_s32_f32): Likewise. + (vcvtnq_s16_f16): Likewise. + (vcvtnq_s32_f32): Likewise. + (vcvtpq_s16_f16): Likewise. + (vcvtpq_s32_f32): Likewise. + (vcvtmq_s16_f16): Likewise. + (vcvtmq_s32_f32): Likewise. + (vmvnq_u8): Likewise. + (vmvnq_u16): Likewise. + (vmvnq_u32): Likewise. + (vdupq_n_u8): Likewise. + (vdupq_n_u16): Likewise. + (vdupq_n_u32): Likewise. + (vclzq_u8): Likewise. + (vclzq_u16): Likewise. + (vclzq_u32): Likewise. + (vaddvq_u8): Likewise. + (vaddvq_u16): Likewise. + (vaddvq_u32): Likewise. + (vrev32q_u8): Likewise. + (vrev32q_u16): Likewise. + (vmovltq_u8): Likewise. + (vmovltq_u16): Likewise. + (vmovlbq_u8): Likewise. + (vmovlbq_u16): Likewise. + (vrev16q_u8): Likewise. + (vaddlvq_u32): Likewise. + (vcvtpq_u16_f16): Likewise. + (vcvtpq_u32_f32): Likewise. + (vcvtnq_u16_f16): Likewise. + (vcvtmq_u16_f16): Likewise. + (vcvtmq_u32_f32): Likewise. + (vcvtaq_u16_f16): Likewise. + (vcvtaq_u32_f32): Likewise. + (__arm_vdupq_n_s8): Define intrinsic. + (__arm_vdupq_n_s16): Likewise. + (__arm_vdupq_n_s32): Likewise. + (__arm_vabsq_s8): Likewise. + (__arm_vabsq_s16): Likewise. + (__arm_vabsq_s32): Likewise. + (__arm_vclsq_s8): Likewise. + (__arm_vclsq_s16): Likewise. + (__arm_vclsq_s32): Likewise. + (__arm_vclzq_s8): Likewise. + (__arm_vclzq_s16): Likewise. + (__arm_vclzq_s32): Likewise. + (__arm_vnegq_s8): Likewise. + (__arm_vnegq_s16): Likewise. + (__arm_vnegq_s32): Likewise. + (__arm_vaddlvq_s32): Likewise. + (__arm_vaddvq_s8): Likewise. + (__arm_vaddvq_s16): Likewise. + (__arm_vaddvq_s32): Likewise. + (__arm_vmovlbq_s8): Likewise. + (__arm_vmovlbq_s16): Likewise. + (__arm_vmovltq_s8): Likewise. + (__arm_vmovltq_s16): Likewise. + (__arm_vmvnq_s8): Likewise. + (__arm_vmvnq_s16): Likewise. + (__arm_vmvnq_s32): Likewise. + (__arm_vrev16q_s8): Likewise. + (__arm_vrev32q_s8): Likewise. + (__arm_vrev32q_s16): Likewise. + (__arm_vqabsq_s8): Likewise. + (__arm_vqabsq_s16): Likewise. + (__arm_vqabsq_s32): Likewise. + (__arm_vqnegq_s8): Likewise. + (__arm_vqnegq_s16): Likewise. + (__arm_vqnegq_s32): Likewise. + (__arm_vmvnq_u8): Likewise. + (__arm_vmvnq_u16): Likewise. + (__arm_vmvnq_u32): Likewise. + (__arm_vdupq_n_u8): Likewise. + (__arm_vdupq_n_u16): Likewise. + (__arm_vdupq_n_u32): Likewise. + (__arm_vclzq_u8): Likewise. + (__arm_vclzq_u16): Likewise. + (__arm_vclzq_u32): Likewise. + (__arm_vaddvq_u8): Likewise. + (__arm_vaddvq_u16): Likewise. + (__arm_vaddvq_u32): Likewise. + (__arm_vrev32q_u8): Likewise. + (__arm_vrev32q_u16): Likewise. + (__arm_vmovltq_u8): Likewise. + (__arm_vmovltq_u16): Likewise. + (__arm_vmovlbq_u8): Likewise. + (__arm_vmovlbq_u16): Likewise. + (__arm_vrev16q_u8): Likewise. + (__arm_vaddlvq_u32): Likewise. + (__arm_vcvtpq_u16_f16): Likewise. + (__arm_vcvtpq_u32_f32): Likewise. + (__arm_vcvtnq_u16_f16): Likewise. + (__arm_vcvtmq_u16_f16): Likewise. + (__arm_vcvtmq_u32_f32): Likewise. + (__arm_vcvtaq_u16_f16): Likewise. + (__arm_vcvtaq_u32_f32): Likewise. + (__arm_vcvtaq_s16_f16): Likewise. + (__arm_vcvtaq_s32_f32): Likewise. + (__arm_vcvtnq_s16_f16): Likewise. + (__arm_vcvtnq_s32_f32): Likewise. + (__arm_vcvtpq_s16_f16): Likewise. + (__arm_vcvtpq_s32_f32): Likewise. + (__arm_vcvtmq_s16_f16): Likewise. + (__arm_vcvtmq_s32_f32): Likewise. + (vdupq_n): Define polymorphic variant. + (vabsq): Likewise. + (vclsq): Likewise. + (vclzq): Likewise. + (vnegq): Likewise. + (vaddlvq): Likewise. + (vaddvq): Likewise. + (vmovlbq): Likewise. + (vmovltq): Likewise. + (vmvnq): Likewise. + (vrev16q): Likewise. + (vrev32q): Likewise. + (vqabsq): Likewise. + (vqnegq): Likewise. + * config/arm/arm_mve_builtins.def (UNOP_SNONE_SNONE): Use it. + (UNOP_SNONE_NONE): Likewise. + (UNOP_UNONE_UNONE): Likewise. + (UNOP_UNONE_NONE): Likewise. + * config/arm/constraints.md (e): Define new constriant to allow only + even registers. + * config/arm/mve.md (mve_vqabsq_s): Define RTL pattern. + (mve_vnegq_s): Likewise. + (mve_vmvnq_): Likewise. + (mve_vdupq_n_): Likewise. + (mve_vclzq_): Likewise. + (mve_vclsq_s): Likewise. + (mve_vaddvq_): Likewise. + (mve_vabsq_s): Likewise. + (mve_vrev32q_): Likewise. + (mve_vmovltq_): Likewise. + (mve_vmovlbq_): Likewise. + (mve_vcvtpq_): Likewise. + (mve_vcvtnq_): Likewise. + (mve_vcvtmq_): Likewise. + (mve_vcvtaq_): Likewise. + (mve_vrev16q_v16qi): Likewise. + (mve_vaddlvq_v4si): Likewise. + 2020-03-17 Jakub Jelinek * lra-spills.c (remove_pseudos): Fix up duplicated word issue in diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index c7453412959..fb55f73c62b 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1167,6 +1167,7 @@ enum reg_class BASE_REGS, HI_REGS, CALLER_SAVE_REGS, + EVEN_REG, GENERAL_REGS, CORE_REGS, VFP_D0_D7_REGS, @@ -1195,6 +1196,7 @@ enum reg_class "BASE_REGS", \ "HI_REGS", \ "CALLER_SAVE_REGS", \ + "EVEN_REG", \ "GENERAL_REGS", \ "CORE_REGS", \ "VFP_D0_D7_REGS", \ @@ -1222,6 +1224,7 @@ enum reg_class { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ + { 0x00005555, 0x00000000, 0x00000000, 0x00000000 }, /* EVEN_REGS. */ \ { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 14dd4172011..912849f0acd 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -108,20 +108,90 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t; #define vcvtq_f32_s32(__a) __arm_vcvtq_f32_s32(__a) #define vcvtq_f16_u16(__a) __arm_vcvtq_f16_u16(__a) #define vcvtq_f32_u32(__a) __arm_vcvtq_f32_u32(__a) +#define vdupq_n_s8(__a) __arm_vdupq_n_s8(__a) +#define vdupq_n_s16(__a) __arm_vdupq_n_s16(__a) +#define vdupq_n_s32(__a) __arm_vdupq_n_s32(__a) +#define vabsq_s8(__a) __arm_vabsq_s8(__a) +#define vabsq_s16(__a) __arm_vabsq_s16(__a) +#define vabsq_s32(__a) __arm_vabsq_s32(__a) +#define vclsq_s8(__a) __arm_vclsq_s8(__a) +#define vclsq_s16(__a) __arm_vclsq_s16(__a) +#define vclsq_s32(__a) __arm_vclsq_s32(__a) +#define vclzq_s8(__a) __arm_vclzq_s8(__a) +#define vclzq_s16(__a) __arm_vclzq_s16(__a) +#define vclzq_s32(__a) __arm_vclzq_s32(__a) +#define vnegq_s8(__a) __arm_vnegq_s8(__a) +#define vnegq_s16(__a) __arm_vnegq_s16(__a) +#define vnegq_s32(__a) __arm_vnegq_s32(__a) +#define vaddlvq_s32(__a) __arm_vaddlvq_s32(__a) +#define vaddvq_s8(__a) __arm_vaddvq_s8(__a) +#define vaddvq_s16(__a) __arm_vaddvq_s16(__a) +#define vaddvq_s32(__a) __arm_vaddvq_s32(__a) +#define vmovlbq_s8(__a) __arm_vmovlbq_s8(__a) +#define vmovlbq_s16(__a) __arm_vmovlbq_s16(__a) +#define vmovltq_s8(__a) __arm_vmovltq_s8(__a) +#define vmovltq_s16(__a) __arm_vmovltq_s16(__a) +#define vmvnq_s8(__a) __arm_vmvnq_s8(__a) +#define vmvnq_s16(__a) __arm_vmvnq_s16(__a) +#define vmvnq_s32(__a) __arm_vmvnq_s32(__a) #define vmvnq_n_s16( __imm) __arm_vmvnq_n_s16( __imm) #define vmvnq_n_s32( __imm) __arm_vmvnq_n_s32( __imm) +#define vrev16q_s8(__a) __arm_vrev16q_s8(__a) +#define vrev32q_s8(__a) __arm_vrev32q_s8(__a) +#define vrev32q_s16(__a) __arm_vrev32q_s16(__a) #define vrev64q_s8(__a) __arm_vrev64q_s8(__a) #define vrev64q_s16(__a) __arm_vrev64q_s16(__a) #define vrev64q_s32(__a) __arm_vrev64q_s32(__a) +#define vqabsq_s8(__a) __arm_vqabsq_s8(__a) +#define vqabsq_s16(__a) __arm_vqabsq_s16(__a) +#define vqabsq_s32(__a) __arm_vqabsq_s32(__a) +#define vqnegq_s8(__a) __arm_vqnegq_s8(__a) +#define vqnegq_s16(__a) __arm_vqnegq_s16(__a) +#define vqnegq_s32(__a) __arm_vqnegq_s32(__a) +#define vcvtaq_s16_f16(__a) __arm_vcvtaq_s16_f16(__a) +#define vcvtaq_s32_f32(__a) __arm_vcvtaq_s32_f32(__a) +#define vcvtnq_s16_f16(__a) __arm_vcvtnq_s16_f16(__a) +#define vcvtnq_s32_f32(__a) __arm_vcvtnq_s32_f32(__a) +#define vcvtpq_s16_f16(__a) __arm_vcvtpq_s16_f16(__a) +#define vcvtpq_s32_f32(__a) __arm_vcvtpq_s32_f32(__a) +#define vcvtmq_s16_f16(__a) __arm_vcvtmq_s16_f16(__a) +#define vcvtmq_s32_f32(__a) __arm_vcvtmq_s32_f32(__a) #define vcvtq_s16_f16(__a) __arm_vcvtq_s16_f16(__a) #define vcvtq_s32_f32(__a) __arm_vcvtq_s32_f32(__a) #define vrev64q_u8(__a) __arm_vrev64q_u8(__a) #define vrev64q_u16(__a) __arm_vrev64q_u16(__a) #define vrev64q_u32(__a) __arm_vrev64q_u32(__a) +#define vmvnq_u8(__a) __arm_vmvnq_u8(__a) +#define vmvnq_u16(__a) __arm_vmvnq_u16(__a) +#define vmvnq_u32(__a) __arm_vmvnq_u32(__a) +#define vdupq_n_u8(__a) __arm_vdupq_n_u8(__a) +#define vdupq_n_u16(__a) __arm_vdupq_n_u16(__a) +#define vdupq_n_u32(__a) __arm_vdupq_n_u32(__a) +#define vclzq_u8(__a) __arm_vclzq_u8(__a) +#define vclzq_u16(__a) __arm_vclzq_u16(__a) +#define vclzq_u32(__a) __arm_vclzq_u32(__a) +#define vaddvq_u8(__a) __arm_vaddvq_u8(__a) +#define vaddvq_u16(__a) __arm_vaddvq_u16(__a) +#define vaddvq_u32(__a) __arm_vaddvq_u32(__a) +#define vrev32q_u8(__a) __arm_vrev32q_u8(__a) +#define vrev32q_u16(__a) __arm_vrev32q_u16(__a) +#define vmovltq_u8(__a) __arm_vmovltq_u8(__a) +#define vmovltq_u16(__a) __arm_vmovltq_u16(__a) +#define vmovlbq_u8(__a) __arm_vmovlbq_u8(__a) +#define vmovlbq_u16(__a) __arm_vmovlbq_u16(__a) #define vmvnq_n_u16( __imm) __arm_vmvnq_n_u16( __imm) #define vmvnq_n_u32( __imm) __arm_vmvnq_n_u32( __imm) +#define vrev16q_u8(__a) __arm_vrev16q_u8(__a) +#define vaddlvq_u32(__a) __arm_vaddlvq_u32(__a) #define vcvtq_u16_f16(__a) __arm_vcvtq_u16_f16(__a) #define vcvtq_u32_f32(__a) __arm_vcvtq_u32_f32(__a) +#define vcvtpq_u16_f16(__a) __arm_vcvtpq_u16_f16(__a) +#define vcvtpq_u32_f32(__a) __arm_vcvtpq_u32_f32(__a) +#define vcvtnq_u16_f16(__a) __arm_vcvtnq_u16_f16(__a) +#define vcvtmq_u16_f16(__a) __arm_vcvtmq_u16_f16(__a) +#define vcvtmq_u32_f32(__a) __arm_vcvtmq_u32_f32(__a) +#define vcvtaq_u16_f16(__a) __arm_vcvtaq_u16_f16(__a) +#define vcvtaq_u32_f32(__a) __arm_vcvtaq_u32_f32(__a) #endif __extension__ extern __inline void @@ -178,6 +248,188 @@ __arm_vst4q_u32 (uint32_t * __addr, uint32x4x4_t __value) __builtin_mve_vst4qv4si ((__builtin_neon_si *) __addr, __rv.__o); } +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_s8 (int8_t __a) +{ + return __builtin_mve_vdupq_n_sv16qi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_s16 (int16_t __a) +{ + return __builtin_mve_vdupq_n_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_s32 (int32_t __a) +{ + return __builtin_mve_vdupq_n_sv4si (__a); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_s8 (int8x16_t __a) +{ + return __builtin_mve_vabsq_sv16qi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_s16 (int16x8_t __a) +{ + return __builtin_mve_vabsq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vabsq_s32 (int32x4_t __a) +{ + return __builtin_mve_vabsq_sv4si (__a); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclsq_s8 (int8x16_t __a) +{ + return __builtin_mve_vclsq_sv16qi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclsq_s16 (int16x8_t __a) +{ + return __builtin_mve_vclsq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclsq_s32 (int32x4_t __a) +{ + return __builtin_mve_vclsq_sv4si (__a); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclzq_s8 (int8x16_t __a) +{ + return __builtin_mve_vclzq_sv16qi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclzq_s16 (int16x8_t __a) +{ + return __builtin_mve_vclzq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclzq_s32 (int32x4_t __a) +{ + return __builtin_mve_vclzq_sv4si (__a); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_s8 (int8x16_t __a) +{ + return __builtin_mve_vnegq_sv16qi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_s16 (int16x8_t __a) +{ + return __builtin_mve_vnegq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vnegq_s32 (int32x4_t __a) +{ + return __builtin_mve_vnegq_sv4si (__a); +} + +__extension__ extern __inline int64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddlvq_s32 (int32x4_t __a) +{ + return __builtin_mve_vaddlvq_sv4si (__a); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvq_s8 (int8x16_t __a) +{ + return __builtin_mve_vaddvq_sv16qi (__a); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvq_s16 (int16x8_t __a) +{ + return __builtin_mve_vaddvq_sv8hi (__a); +} + +__extension__ extern __inline int32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvq_s32 (int32x4_t __a) +{ + return __builtin_mve_vaddvq_sv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmovlbq_s8 (int8x16_t __a) +{ + return __builtin_mve_vmovlbq_sv16qi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmovlbq_s16 (int16x8_t __a) +{ + return __builtin_mve_vmovlbq_sv8hi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmovltq_s8 (int8x16_t __a) +{ + return __builtin_mve_vmovltq_sv16qi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmovltq_s16 (int16x8_t __a) +{ + return __builtin_mve_vmovltq_sv8hi (__a); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_s8 (int8x16_t __a) +{ + return __builtin_mve_vmvnq_sv16qi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_s16 (int16x8_t __a) +{ + return __builtin_mve_vmvnq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_s32 (int32x4_t __a) +{ + return __builtin_mve_vmvnq_sv4si (__a); +} + __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_n_s16 (const int16_t __imm) @@ -192,6 +444,27 @@ __arm_vmvnq_n_s32 (const int32_t __imm) return __builtin_mve_vmvnq_n_sv4si (__imm); } +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev16q_s8 (int8x16_t __a) +{ + return __builtin_mve_vrev16q_sv16qi (__a); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev32q_s8 (int8x16_t __a) +{ + return __builtin_mve_vrev32q_sv16qi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev32q_s16 (int16x8_t __a) +{ + return __builtin_mve_vrev32q_sv8hi (__a); +} + __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vrev64q_s8 (int8x16_t __a) @@ -213,6 +486,48 @@ __arm_vrev64q_s32 (int32x4_t __a) return __builtin_mve_vrev64q_sv4si (__a); } +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqabsq_s8 (int8x16_t __a) +{ + return __builtin_mve_vqabsq_sv16qi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqabsq_s16 (int16x8_t __a) +{ + return __builtin_mve_vqabsq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqabsq_s32 (int32x4_t __a) +{ + return __builtin_mve_vqabsq_sv4si (__a); +} + +__extension__ extern __inline int8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqnegq_s8 (int8x16_t __a) +{ + return __builtin_mve_vqnegq_sv16qi (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqnegq_s16 (int16x8_t __a) +{ + return __builtin_mve_vqnegq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vqnegq_s32 (int32x4_t __a) +{ + return __builtin_mve_vqnegq_sv4si (__a); +} + __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vrev64q_u8 (uint8x16_t __a) @@ -234,6 +549,132 @@ __arm_vrev64q_u32 (uint32x4_t __a) return __builtin_mve_vrev64q_uv4si (__a); } +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_u8 (uint8x16_t __a) +{ + return __builtin_mve_vmvnq_uv16qi (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_u16 (uint16x8_t __a) +{ + return __builtin_mve_vmvnq_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmvnq_u32 (uint32x4_t __a) +{ + return __builtin_mve_vmvnq_uv4si (__a); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_u8 (uint8_t __a) +{ + return __builtin_mve_vdupq_n_uv16qi (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_u16 (uint16_t __a) +{ + return __builtin_mve_vdupq_n_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vdupq_n_u32 (uint32_t __a) +{ + return __builtin_mve_vdupq_n_uv4si (__a); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclzq_u8 (uint8x16_t __a) +{ + return __builtin_mve_vclzq_uv16qi (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclzq_u16 (uint16x8_t __a) +{ + return __builtin_mve_vclzq_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vclzq_u32 (uint32x4_t __a) +{ + return __builtin_mve_vclzq_uv4si (__a); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvq_u8 (uint8x16_t __a) +{ + return __builtin_mve_vaddvq_uv16qi (__a); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvq_u16 (uint16x8_t __a) +{ + return __builtin_mve_vaddvq_uv8hi (__a); +} + +__extension__ extern __inline uint32_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddvq_u32 (uint32x4_t __a) +{ + return __builtin_mve_vaddvq_uv4si (__a); +} + +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev32q_u8 (uint8x16_t __a) +{ + return __builtin_mve_vrev32q_uv16qi (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev32q_u16 (uint16x8_t __a) +{ + return __builtin_mve_vrev32q_uv8hi (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmovltq_u8 (uint8x16_t __a) +{ + return __builtin_mve_vmovltq_uv16qi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmovltq_u16 (uint16x8_t __a) +{ + return __builtin_mve_vmovltq_uv8hi (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmovlbq_u8 (uint8x16_t __a) +{ + return __builtin_mve_vmovlbq_uv16qi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vmovlbq_u16 (uint16x8_t __a) +{ + return __builtin_mve_vmovlbq_uv8hi (__a); +} + __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __arm_vmvnq_n_u16 (const int __imm) @@ -248,6 +689,20 @@ __arm_vmvnq_n_u32 (const int __imm) return __builtin_mve_vmvnq_n_uv4si (__imm); } +__extension__ extern __inline uint8x16_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vrev16q_u8 (uint8x16_t __a) +{ + return __builtin_mve_vrev16q_uv16qi (__a); +} + +__extension__ extern __inline uint64_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vaddlvq_u32 (uint32x4_t __a) +{ + return __builtin_mve_vaddlvq_uv4si (__a); +} + #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ __extension__ extern __inline void @@ -485,6 +940,111 @@ __arm_vcvtq_u32_f32 (float32x4_t __a) return __builtin_mve_vcvtq_from_f_uv4si (__a); } +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtpq_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_u32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtpq_uv4si (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtnq_uv8hi (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtmq_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_u32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtmq_uv4si (__a); +} + +__extension__ extern __inline uint16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_u16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtaq_uv8hi (__a); +} + +__extension__ extern __inline uint32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_u32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtaq_uv4si (__a); +} + + __extension__ extern __inline int16x8_t + __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtaq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtaq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtaq_sv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtnq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtnq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtnq_sv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtpq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtpq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtpq_sv4si (__a); +} + +__extension__ extern __inline int16x8_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_s16_f16 (float16x8_t __a) +{ + return __builtin_mve_vcvtmq_sv8hi (__a); +} + +__extension__ extern __inline int32x4_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__arm_vcvtmq_s32_f32 (float32x4_t __a) +{ + return __builtin_mve_vcvtmq_sv4si (__a); +} + #endif enum { @@ -735,24 +1295,40 @@ extern void *__ARM_undef; #define vrev64q(p0) __arm_vrev64q(p0) #define __arm_vrev64q(p0) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev64q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev64q_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vrev64q_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev64q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev64q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrev64q_u32 (__ARM_mve_coerce(__p0, uint32x4_t)), \ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev64q_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ int (*)[__ARM_mve_type_float32x4_t]: __arm_vrev64q_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) #define vnegq(p0) __arm_vnegq(p0) #define __arm_vnegq(p0) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vnegq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vnegq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vnegq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ int (*)[__ARM_mve_type_float16x8_t]: __arm_vnegq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ int (*)[__ARM_mve_type_float32x4_t]: __arm_vnegq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) #define vabsq(p0) __arm_vabsq(p0) #define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vabsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vabsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vabsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ int (*)[__ARM_mve_type_float16x8_t]: __arm_vabsq_f16 (__ARM_mve_coerce(__p0, float16x8_t)), \ int (*)[__ARM_mve_type_float32x4_t]: __arm_vabsq_f32 (__ARM_mve_coerce(__p0, float32x4_t)));}) #define vrev32q(p0) __arm_vrev32q(p0) #define __arm_vrev32q(p0) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev32q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev32q_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev32q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev32q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ int (*)[__ARM_mve_type_float16x8_t]: __arm_vrev32q_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) #define vcvtbq_f32(p0) __arm_vcvtbq_f32(p0) @@ -765,6 +1341,69 @@ extern void *__ARM_undef; _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ int (*)[__ARM_mve_type_float16x8_t]: __arm_vcvttq_f32_f16 (__ARM_mve_coerce(__p0, float16x8_t)));}) +#define vrev16q(p0) __arm_vrev16q(p0) +#define __arm_vrev16q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev16q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev16q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)));}) + +#define vqabsq(p0) __arm_vqabsq(p0) +#define __arm_vqabsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqabsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqabsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqabsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + +#define vqnegq(p0) __arm_vqnegq(p0) +#define __arm_vqnegq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqnegq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqnegq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqnegq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + +#define vmvnq(p0) __arm_vmvnq(p0) +#define __arm_vmvnq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmvnq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmvnq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vmvnq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmvnq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmvnq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vmvnq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + +#define vmovlbq(p0) __arm_vmovlbq(p0) +#define __arm_vmovlbq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovlbq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovlbq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovlbq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovlbq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)));}) + +#define vmovltq(p0) __arm_vmovltq(p0) +#define __arm_vmovltq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovltq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovltq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovltq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovltq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)));}) + +#define vclzq(p0) __arm_vclzq(p0) +#define __arm_vclzq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vclzq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vclzq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vclzq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vclzq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vclzq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vclzq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + +#define vclsq(p0) __arm_vclsq(p0) +#define __arm_vclsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vclsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vclsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vclsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + #define vcvtq(p0) __arm_vcvtq(p0) #define __arm_vcvtq(p0) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ @@ -786,6 +1425,93 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16_t_ptr][__ARM_mve_type_uint16x8x4_t]: __arm_vst4q_u16 (__ARM_mve_coerce(__p0, uint16_t *), __ARM_mve_coerce(__p1, uint16x8x4_t)), \ int (*)[__ARM_mve_type_uint32_t_ptr][__ARM_mve_type_uint32x4x4_t]: __arm_vst4q_u32 (__ARM_mve_coerce(__p0, uint32_t *), __ARM_mve_coerce(__p1, uint32x4x4_t)));}) +#define vabsq(p0) __arm_vabsq(p0) +#define __arm_vabsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vabsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vabsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vabsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + +#define vclsq(p0) __arm_vclsq(p0) +#define __arm_vclsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vclsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vclsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vclsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + +#define vclzq(p0) __arm_vclzq(p0) +#define __arm_vclzq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vclzq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vclzq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vclzq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vclzq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vclzq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vclzq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + +#define vnegq(p0) __arm_vnegq(p0) +#define __arm_vnegq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vnegq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vnegq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vnegq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + +#define vaddlvq(p0) __arm_vaddlvq(p0) +#define __arm_vaddlvq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vaddlvq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vaddlvq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + +#define vaddvq(p0) __arm_vaddvq(p0) +#define __arm_vaddvq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vaddvq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vaddvq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vaddvq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vaddvq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vaddvq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vaddvq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + +#define vmovlbq(p0) __arm_vmovlbq(p0) +#define __arm_vmovlbq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovlbq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovlbq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovlbq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovlbq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)));}) + +#define vmovltq(p0) __arm_vmovltq(p0) +#define __arm_vmovltq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmovltq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmovltq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmovltq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmovltq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)));}) + +#define vmvnq(p0) __arm_vmvnq(p0) +#define __arm_vmvnq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vmvnq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vmvnq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vmvnq_s32 (__ARM_mve_coerce(__p0, int32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vmvnq_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vmvnq_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ + int (*)[__ARM_mve_type_uint32x4_t]: __arm_vmvnq_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) + +#define vrev16q(p0) __arm_vrev16q(p0) +#define __arm_vrev16q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev16q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev16q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)));}) + +#define vrev32q(p0) __arm_vrev32q(p0) +#define __arm_vrev32q(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vrev32q_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vrev32q_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_uint8x16_t]: __arm_vrev32q_u8 (__ARM_mve_coerce(__p0, uint8x16_t)), \ + int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev32q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)));}) + #define vrev64q(p0) __arm_vrev64q(p0) #define __arm_vrev64q(p0) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ @@ -796,6 +1522,20 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint16x8_t]: __arm_vrev64q_u16 (__ARM_mve_coerce(__p0, uint16x8_t)), \ int (*)[__ARM_mve_type_uint32x4_t]: __arm_vrev64q_u32 (__ARM_mve_coerce(__p0, uint32x4_t)));}) +#define vqabsq(p0) __arm_vqabsq(p0) +#define __arm_vqabsq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqabsq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqabsq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqabsq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + +#define vqnegq(p0) __arm_vqnegq(p0) +#define __arm_vqnegq(p0) ({ __typeof(p0) __p0 = (p0); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ + int (*)[__ARM_mve_type_int8x16_t]: __arm_vqnegq_s8 (__ARM_mve_coerce(__p0, int8x16_t)), \ + int (*)[__ARM_mve_type_int16x8_t]: __arm_vqnegq_s16 (__ARM_mve_coerce(__p0, int16x8_t)), \ + int (*)[__ARM_mve_type_int32x4_t]: __arm_vqnegq_s32 (__ARM_mve_coerce(__p0, int32x4_t)));}) + #endif /* MVE Floating point. */ #ifdef __cplusplus diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index d325f36aff4..44807d6e8c4 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -35,8 +35,39 @@ VAR1 (UNOP_NONE_NONE, vcvtbq_f32_f16, v4sf) VAR2 (UNOP_NONE_SNONE, vcvtq_to_f_s, v8hf, v4sf) VAR2 (UNOP_NONE_UNONE, vcvtq_to_f_u, v8hf, v4sf) VAR3 (UNOP_SNONE_SNONE, vrev64q_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vqnegq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vqabsq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vnegq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vmvnq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vdupq_n_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vclzq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vclsq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vaddvq_s, v16qi, v8hi, v4si) +VAR3 (UNOP_SNONE_SNONE, vabsq_s, v16qi, v8hi, v4si) +VAR2 (UNOP_SNONE_SNONE, vrev32q_s, v16qi, v8hi) +VAR2 (UNOP_SNONE_SNONE, vmovltq_s, v16qi, v8hi) +VAR2 (UNOP_SNONE_SNONE, vmovlbq_s, v16qi, v8hi) VAR2 (UNOP_SNONE_NONE, vcvtq_from_f_s, v8hi, v4si) +VAR2 (UNOP_SNONE_NONE, vcvtpq_s, v8hi, v4si) +VAR2 (UNOP_SNONE_NONE, vcvtnq_s, v8hi, v4si) +VAR2 (UNOP_SNONE_NONE, vcvtmq_s, v8hi, v4si) +VAR2 (UNOP_SNONE_NONE, vcvtaq_s, v8hi, v4si) VAR2 (UNOP_SNONE_IMM, vmvnq_n_s, v8hi, v4si) +VAR1 (UNOP_SNONE_SNONE, vrev16q_s, v16qi) +VAR1 (UNOP_SNONE_SNONE, vaddlvq_s, v4si) VAR3 (UNOP_UNONE_UNONE, vrev64q_u, v16qi, v8hi, v4si) +VAR3 (UNOP_UNONE_UNONE, vmvnq_u, v16qi, v8hi, v4si) +VAR3 (UNOP_UNONE_UNONE, vdupq_n_u, v16qi, v8hi, v4si) +VAR3 (UNOP_UNONE_UNONE, vclzq_u, v16qi, v8hi, v4si) +VAR3 (UNOP_UNONE_UNONE, vaddvq_u, v16qi, v8hi, v4si) +VAR2 (UNOP_UNONE_UNONE, vrev32q_u, v16qi, v8hi) +VAR2 (UNOP_UNONE_UNONE, vmovltq_u, v16qi, v8hi) +VAR2 (UNOP_UNONE_UNONE, vmovlbq_u, v16qi, v8hi) VAR2 (UNOP_UNONE_NONE, vcvtq_from_f_u, v8hi, v4si) +VAR2 (UNOP_UNONE_NONE, vcvtpq_u, v8hi, v4si) +VAR2 (UNOP_UNONE_NONE, vcvtnq_u, v8hi, v4si) +VAR2 (UNOP_UNONE_NONE, vcvtmq_u, v8hi, v4si) +VAR2 (UNOP_UNONE_NONE, vcvtaq_u, v8hi, v4si) VAR2 (UNOP_UNONE_IMM, vmvnq_n_u, v8hi, v4si) +VAR1 (UNOP_UNONE_UNONE, vrev16q_u, v16qi) +VAR1 (UNOP_UNONE_UNONE, vaddlvq_u, v4si) diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index bf8f4ff1e5d..492dc963419 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -49,6 +49,10 @@ (define_register_constraint "Uf" "TARGET_HAVE_MVE ? VFPCC_REG : NO_REGS" "MVE FPCCR register") +(define_register_constraint "e" "TARGET_HAVE_MVE ? EVEN_REG : NO_REGS" + "MVE EVEN registers @code{r0}, @code{r2}, @code{r4}, @code{r6}, @code{r8}, + @code{r10}, @code{r12}, @code{r14}") + (define_register_constraint "t" "TARGET_32BIT ? VFP_LO_REGS : NO_REGS" "The VFP registers @code{s0}-@code{s31}.") diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index a58cfb28795..dafdc1cf16e 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -22,26 +22,55 @@ (define_mode_iterator MVE_types [V16QI V8HI V4SI V2DI TI V8HF V4SF V2DF]) (define_mode_iterator MVE_VLD_ST [V16QI V8HI V4SI V8HF V4SF]) (define_mode_iterator MVE_0 [V8HF V4SF]) +(define_mode_iterator MVE_3 [V16QI V8HI]) (define_mode_iterator MVE_2 [V16QI V8HI V4SI]) (define_mode_iterator MVE_5 [V8HI V4SI]) (define_c_enum "unspec" [VST4Q VRNDXQ_F VRNDQ_F VRNDPQ_F VRNDNQ_F VRNDMQ_F VRNDAQ_F VREV64Q_F VNEGQ_F VDUPQ_N_F VABSQ_F VREV32Q_F - VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S - VCVTQ_TO_F_U VMVNQ_N_S VMVNQ_N_U VREV64Q_S VREV64Q_U - VCVTQ_FROM_F_S VCVTQ_FROM_F_U]) + VCVTTQ_F32_F16 VCVTBQ_F32_F16 VCVTQ_TO_F_S VQNEGQ_S + VCVTQ_TO_F_U VREV16Q_S VREV16Q_U VADDLVQ_S VMVNQ_N_S + VMVNQ_N_U VCVTAQ_S VCVTAQ_U VREV64Q_S VREV64Q_U + VQABSQ_S VNEGQ_S VMVNQ_S VMVNQ_U VDUPQ_N_U VDUPQ_N_S + VCLZQ_U VCLZQ_S VCLSQ_S VADDVQ_S VADDVQ_U VABSQ_S + VREV32Q_U VREV32Q_S VMOVLTQ_U VMOVLTQ_S VMOVLBQ_S + VMOVLBQ_U VCVTQ_FROM_F_S VCVTQ_FROM_F_U VCVTPQ_S + VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U + VADDLVQ_U]) (define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF") (V8HF "V8HI") (V4SF "V4SI")]) -(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VMVNQ_N_S "s") - (VMVNQ_N_U "u") (VREV64Q_U "u") (VREV64Q_S "s") - (VCVTQ_FROM_F_S "s") (VCVTQ_FROM_F_U "u")]) +(define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U "u") (VREV16Q_S "s") + (VREV16Q_U "u") (VMVNQ_N_S "s") (VMVNQ_N_U "u") + (VCVTAQ_U "u") (VCVTAQ_S "s") (VREV64Q_S "s") + (VREV64Q_U "u") (VMVNQ_S "s") (VMVNQ_U "u") + (VDUPQ_N_U "u") (VDUPQ_N_S"s") (VADDVQ_S "s") + (VADDVQ_U "u") (VADDVQ_S "s") (VADDVQ_U "u") + (VMOVLTQ_U "u") (VMOVLTQ_S "s") (VMOVLBQ_S "s") + (VMOVLBQ_U "u") (VCVTQ_FROM_F_S "s") (VCVTQ_FROM_F_U "u") + (VCVTPQ_S "s") (VCVTPQ_U "u") (VCVTNQ_S "s") + (VCVTNQ_U "u") (VCVTMQ_S "s") (VCVTMQ_U "u") + (VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u") + (VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s")]) (define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U]) (define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S]) (define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U]) (define_int_iterator VCVTQ_FROM_F [VCVTQ_FROM_F_S VCVTQ_FROM_F_U]) +(define_int_iterator VREV16Q [VREV16Q_U VREV16Q_S]) +(define_int_iterator VCVTAQ [VCVTAQ_U VCVTAQ_S]) +(define_int_iterator VMVNQ [VMVNQ_U VMVNQ_S]) +(define_int_iterator VDUPQ_N [VDUPQ_N_U VDUPQ_N_S]) +(define_int_iterator VCLZQ [VCLZQ_U VCLZQ_S]) +(define_int_iterator VADDVQ [VADDVQ_U VADDVQ_S]) +(define_int_iterator VREV32Q [VREV32Q_U VREV32Q_S]) +(define_int_iterator VMOVLBQ [VMOVLBQ_S VMOVLBQ_U]) +(define_int_iterator VMOVLTQ [VMOVLTQ_U VMOVLTQ_S]) +(define_int_iterator VCVTPQ [VCVTPQ_S VCVTPQ_U]) +(define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U]) +(define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U]) +(define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S]) (define_insn "*mve_mov" [(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us") @@ -362,6 +391,228 @@ "vcvt.%#.f%# %q0, %q1" [(set_attr "type" "mve_move") ]) +;; [vqnegq_s]) +;; +(define_insn "mve_vqnegq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] + VQNEGQ_S)) + ] + "TARGET_HAVE_MVE" + "vqneg.s%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vqabsq_s]) +;; +(define_insn "mve_vqabsq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] + VQABSQ_S)) + ] + "TARGET_HAVE_MVE" + "vqabs.s%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vnegq_s]) +;; +(define_insn "mve_vnegq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] + VNEGQ_S)) + ] + "TARGET_HAVE_MVE" + "vneg.s%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmvnq_u, vmvnq_s]) +;; +(define_insn "mve_vmvnq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] + VMVNQ)) + ] + "TARGET_HAVE_MVE" + "vmvn %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vdupq_n_u, vdupq_n_s]) +;; +(define_insn "mve_vdupq_n_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand: 1 "s_register_operand" "r")] + VDUPQ_N)) + ] + "TARGET_HAVE_MVE" + "vdup.%# %q0, %1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vclzq_u, vclzq_s]) +;; +(define_insn "mve_vclzq_" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] + VCLZQ)) + ] + "TARGET_HAVE_MVE" + "vclz.i%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vclsq_s]) +;; +(define_insn "mve_vclsq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] + VCLSQ_S)) + ] + "TARGET_HAVE_MVE" + "vcls.s%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vaddvq_s, vaddvq_u]) +;; +(define_insn "mve_vaddvq_" + [ + (set (match_operand:SI 0 "s_register_operand" "=e") + (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")] + VADDVQ)) + ] + "TARGET_HAVE_MVE" + "vaddv.%#\t%0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vabsq_s]) +;; +(define_insn "mve_vabsq_s" + [ + (set (match_operand:MVE_2 0 "s_register_operand" "=w") + (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")] + VABSQ_S)) + ] + "TARGET_HAVE_MVE" + "vabs.s%#\t%q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vrev32q_u, vrev32q_s]) +;; +(define_insn "mve_vrev32q_" + [ + (set (match_operand:MVE_3 0 "s_register_operand" "=w") + (unspec:MVE_3 [(match_operand:MVE_3 1 "s_register_operand" "w")] + VREV32Q)) + ] + "TARGET_HAVE_MVE" + "vrev32.%#\t%q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmovltq_u, vmovltq_s]) +;; +(define_insn "mve_vmovltq_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:MVE_3 1 "s_register_operand" "w")] + VMOVLTQ)) + ] + "TARGET_HAVE_MVE" + "vmovlt.%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vmovlbq_s, vmovlbq_u]) +;; +(define_insn "mve_vmovlbq_" + [ + (set (match_operand: 0 "s_register_operand" "=w") + (unspec: [(match_operand:MVE_3 1 "s_register_operand" "w")] + VMOVLBQ)) + ] + "TARGET_HAVE_MVE" + "vmovlb.%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtpq_s, vcvtpq_u]) +;; +(define_insn "mve_vcvtpq_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand: 1 "s_register_operand" "w")] + VCVTPQ)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvtp.%#.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtnq_s, vcvtnq_u]) +;; +(define_insn "mve_vcvtnq_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand: 1 "s_register_operand" "w")] + VCVTNQ)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvtn.%#.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtmq_s, vcvtmq_u]) +;; +(define_insn "mve_vcvtmq_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand: 1 "s_register_operand" "w")] + VCVTMQ)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvtm.%#.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vcvtaq_u, vcvtaq_s]) +;; +(define_insn "mve_vcvtaq_" + [ + (set (match_operand:MVE_5 0 "s_register_operand" "=w") + (unspec:MVE_5 [(match_operand: 1 "s_register_operand" "w")] + VCVTAQ)) + ] + "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" + "vcvta.%#.f%# %q0, %q1" + [(set_attr "type" "mve_move") +]) ;; ;; [vmvnq_n_u, vmvnq_n_s]) @@ -376,3 +627,31 @@ "vmvn.i%# %q0, %1" [(set_attr "type" "mve_move") ]) + +;; +;; [vrev16q_u, vrev16q_s]) +;; +(define_insn "mve_vrev16q_v16qi" + [ + (set (match_operand:V16QI 0 "s_register_operand" "=w") + (unspec:V16QI [(match_operand:V16QI 1 "s_register_operand" "w")] + VREV16Q)) + ] + "TARGET_HAVE_MVE" + "vrev16.8 %q0, %q1" + [(set_attr "type" "mve_move") +]) + +;; +;; [vaddlvq_s vaddlvq_u]) +;; +(define_insn "mve_vaddlvq_v4si" + [ + (set (match_operand:DI 0 "s_register_operand" "=r") + (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")] + VADDLVQ)) + ] + "TARGET_HAVE_MVE" + "vaddlv.32 %Q0, %R0, %q1" + [(set_attr "type" "mve_move") +]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index acf982f7b15..b360cff2484 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,78 @@ +2020-03-17 Andre Vieira + Mihail Ionescu + Srinath Parvathaneni + + * gcc.target/arm/mve/intrinsics/vabsq_s16.c: New test. + * gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddlvq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddlvq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vaddvq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclsq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclsq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclsq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vclzq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_n_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_n_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_n_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_n_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_n_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vdupq_n_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovlbq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovlbq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovlbq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovlbq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovltq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovltq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovltq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmovltq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_u32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vmvnq_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vnegq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqabsq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqabsq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqabsq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqnegq_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqnegq_s32.c: Likewise. + * gcc.target/arm/mve/intrinsics/vqnegq_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev16q_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev16q_u8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_s16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_s8.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_u16.c: Likewise. + * gcc.target/arm/mve/intrinsics/vrev32q_u8.c: Likewise. + 2020-03-17 Mihail Ionescu * gcc.target/arm/multilib.exp: Add new v8.1-M entry. diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c new file mode 100644 index 00000000000..e19f2a3c6e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vabsq_s16 (a); +} + +/* { dg-final { scan-assembler "vabs.s16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vabsq (a); +} + +/* { dg-final { scan-assembler "vabs.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c new file mode 100644 index 00000000000..b639df40765 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vabsq_s32 (a); +} + +/* { dg-final { scan-assembler "vabs.s32" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vabsq (a); +} + +/* { dg-final { scan-assembler "vabs.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c new file mode 100644 index 00000000000..32a7a8688dd --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vabsq_s8 (a); +} + +/* { dg-final { scan-assembler "vabs.s8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vabsq (a); +} + +/* { dg-final { scan-assembler "vabs.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c new file mode 100644 index 00000000000..491034b600f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int64_t +foo (int32x4_t a) +{ + return vaddlvq_s32 (a); +} + +/* { dg-final { scan-assembler "vaddlv.s32" } } */ + +int64_t +foo1 (int32x4_t a) +{ + return vaddlvq_s32 (a); +} + +/* { dg-final { scan-assembler "vaddlv.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c new file mode 100644 index 00000000000..40d064e6728 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddlvq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint64_t +foo (uint32x4_t a) +{ + return vaddlvq_u32 (a); +} + +/* { dg-final { scan-assembler "vaddlv.u32" } } */ + +uint64_t +foo1 (uint32x4_t a) +{ + return vaddlvq (a); +} + +/* { dg-final { scan-assembler "vaddlv.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c new file mode 100644 index 00000000000..3696e970514 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int16x8_t a) +{ + return vaddvq_s16 (a); +} + +/* { dg-final { scan-assembler "vaddv.s16" } } */ + +int32_t +foo1 (int16x8_t a) +{ + return vaddvq_s16 (a); +} + +/* { dg-final { scan-assembler "vaddv.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c new file mode 100644 index 00000000000..b41ec7e9c66 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int32x4_t a) +{ + return vaddvq_s32 (a); +} + +/* { dg-final { scan-assembler "vaddv.s32" } } */ + +int32_t +foo1 (int32x4_t a) +{ + return vaddvq_s32 (a); +} + +/* { dg-final { scan-assembler "vaddv.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c new file mode 100644 index 00000000000..4eeea5318e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32_t +foo (int8x16_t a) +{ + return vaddvq_s8 (a); +} + +/* { dg-final { scan-assembler "vaddv.s8" } } */ + +int32_t +foo1 (int8x16_t a) +{ + return vaddvq (a); +} + +/* { dg-final { scan-assembler "vaddv.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c new file mode 100644 index 00000000000..157e640d25f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint16x8_t a) +{ + return vaddvq_u16 (a); +} + +/* { dg-final { scan-assembler "vaddv.u16" } } */ + +uint32_t +foo1 (uint16x8_t a) +{ + return vaddvq (a); +} + +/* { dg-final { scan-assembler "vaddv.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c new file mode 100644 index 00000000000..befca64f813 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint32x4_t a) +{ + return vaddvq_u32 (a); +} + +/* { dg-final { scan-assembler "vaddv.u32" } } */ + +uint32_t +foo1 (uint32x4_t a) +{ + return vaddvq (a); +} + +/* { dg-final { scan-assembler "vaddv.u32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c new file mode 100644 index 00000000000..e6837f9f293 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddvq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32_t +foo (uint8x16_t a) +{ + return vaddvq_u8 (a); +} + +/* { dg-final { scan-assembler "vaddv.u8" } } */ + +uint32_t +foo1 (uint8x16_t a) +{ + return vaddvq (a); +} + +/* { dg-final { scan-assembler "vaddv.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c new file mode 100644 index 00000000000..ab3981b8f0c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vclsq_s16 (a); +} + +/* { dg-final { scan-assembler "vcls.s16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vclsq (a); +} + +/* { dg-final { scan-assembler "vcls.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c new file mode 100644 index 00000000000..c02da23da04 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vclsq_s32 (a); +} + +/* { dg-final { scan-assembler "vcls.s32" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vclsq (a); +} + +/* { dg-final { scan-assembler "vcls.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c new file mode 100644 index 00000000000..9f8d4523fde --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vclsq_s8 (a); +} + +/* { dg-final { scan-assembler "vcls.s8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vclsq (a); +} + +/* { dg-final { scan-assembler "vcls.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c new file mode 100644 index 00000000000..4c9f64fcbf9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vclzq_s16 (a); +} + +/* { dg-final { scan-assembler "vclz.i16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vclzq (a); +} + +/* { dg-final { scan-assembler "vclz.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c new file mode 100644 index 00000000000..9281b94175b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vclzq_s32 (a); +} + +/* { dg-final { scan-assembler "vclz.i32" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vclzq (a); +} + +/* { dg-final { scan-assembler "vclz.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c new file mode 100644 index 00000000000..4aa7d549b36 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vclzq_s8 (a); +} + +/* { dg-final { scan-assembler "vclz.i8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vclzq (a); +} + +/* { dg-final { scan-assembler "vclz.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c new file mode 100644 index 00000000000..e842b75e6b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a) +{ + return vclzq_u16 (a); +} + +/* { dg-final { scan-assembler "vclz.i16" } } */ + +uint16x8_t +foo1 (uint16x8_t a) +{ + return vclzq (a); +} + +/* { dg-final { scan-assembler "vclz.i16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c new file mode 100644 index 00000000000..917818445d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a) +{ + return vclzq_u32 (a); +} + +/* { dg-final { scan-assembler "vclz.i32" } } */ + +uint32x4_t +foo1 (uint32x4_t a) +{ + return vclzq (a); +} + +/* { dg-final { scan-assembler "vclz.i32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c new file mode 100644 index 00000000000..5726728ff6a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a) +{ + return vclzq_u8 (a); +} + +/* { dg-final { scan-assembler "vclz.i8" } } */ + +uint8x16_t +foo1 (uint8x16_t a) +{ + return vclzq (a); +} + +/* { dg-final { scan-assembler "vclz.i8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c new file mode 100644 index 00000000000..9fa6037e533 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (float16x8_t a) +{ + return vcvtaq_s16_f16 (a); +} + +/* { dg-final { scan-assembler "vcvta.s16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c new file mode 100644 index 00000000000..bdf00b9ee6b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (float32x4_t a) +{ + return vcvtaq_s32_f32 (a); +} + +/* { dg-final { scan-assembler "vcvta.s32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c new file mode 100644 index 00000000000..ab27154c013 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (float16x8_t a) +{ + return vcvtaq_u16_f16 (a); +} + +/* { dg-final { scan-assembler "vcvta.u16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c new file mode 100644 index 00000000000..daf0ff0dd27 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (float32x4_t a) +{ + return vcvtaq_u32_f32 (a); +} + +/* { dg-final { scan-assembler "vcvta.u32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c new file mode 100644 index 00000000000..75134ddafb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (float16x8_t a) +{ + return vcvtmq_s16_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtm.s16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c new file mode 100644 index 00000000000..b4066c966a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (float32x4_t a) +{ + return vcvtmq_s32_f32 (a); +} + +/* { dg-final { scan-assembler "vcvtm.s32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c new file mode 100644 index 00000000000..a5842bce098 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (float16x8_t a) +{ + return vcvtmq_u16_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtm.u16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c new file mode 100644 index 00000000000..03018e2fdf2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (float32x4_t a) +{ + return vcvtmq_u32_f32 (a); +} + +/* { dg-final { scan-assembler "vcvtm.u32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c new file mode 100644 index 00000000000..41b31571397 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (float16x8_t a) +{ + return vcvtnq_s16_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtn.s16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c new file mode 100644 index 00000000000..db921d9c9be --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (float32x4_t a) +{ + return vcvtnq_s32_f32 (a); +} + +/* { dg-final { scan-assembler "vcvtn.s32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c new file mode 100644 index 00000000000..ac446cb238b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (float16x8_t a) +{ + return vcvtnq_u16_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtn.u16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c new file mode 100644 index 00000000000..6c2c1fe152e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (float16x8_t a) +{ + return vcvtpq_s16_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtp.s16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c new file mode 100644 index 00000000000..0b554b35133 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (float32x4_t a) +{ + return vcvtpq_s32_f32 (a); +} + +/* { dg-final { scan-assembler "vcvtp.s32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c new file mode 100644 index 00000000000..27dcb7d1a40 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (float16x8_t a) +{ + return vcvtpq_u16_f16 (a); +} + +/* { dg-final { scan-assembler "vcvtp.u16.f16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c new file mode 100644 index 00000000000..b3a75c37a5c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (float32x4_t a) +{ + return vcvtpq_u32_f32 (a); +} + +/* { dg-final { scan-assembler "vcvtp.u32.f32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c new file mode 100644 index 00000000000..8e5a3e6f2a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16_t a) +{ + return vdupq_n_s16 (a); +} + +/* { dg-final { scan-assembler "vdup.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c new file mode 100644 index 00000000000..71da1428a7a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32_t a) +{ + return vdupq_n_s32 (a); +} + +/* { dg-final { scan-assembler "vdup.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c new file mode 100644 index 00000000000..d80138d500c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8_t a) +{ + return vdupq_n_s8 (a); +} + +/* { dg-final { scan-assembler "vdup.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c new file mode 100644 index 00000000000..5fe7f1502a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16_t a) +{ + return vdupq_n_u16 (a); +} + +/* { dg-final { scan-assembler "vdup.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c new file mode 100644 index 00000000000..65dab51aab7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32_t a) +{ + return vdupq_n_u32 (a); +} + +/* { dg-final { scan-assembler "vdup.32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c new file mode 100644 index 00000000000..72e200999f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8_t a) +{ + return vdupq_n_u8 (a); +} + +/* { dg-final { scan-assembler "vdup.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c new file mode 100644 index 00000000000..8c1a444b608 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16x8_t a) +{ + return vmovlbq_s16 (a); +} + +/* { dg-final { scan-assembler "vmovlb.s16" } } */ + +int32x4_t +foo1 (int16x8_t a) +{ + return vmovlbq (a); +} + +/* { dg-final { scan-assembler "vmovlb.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c new file mode 100644 index 00000000000..9ca36f1d492 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8x16_t a) +{ + return vmovlbq_s8 (a); +} + +/* { dg-final { scan-assembler "vmovlb.s8" } } */ + +int16x8_t +foo1 (int8x16_t a) +{ + return vmovlbq (a); +} + +/* { dg-final { scan-assembler "vmovlb.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c new file mode 100644 index 00000000000..9b537bf20f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16x8_t a) +{ + return vmovlbq_u16 (a); +} + +/* { dg-final { scan-assembler "vmovlb.u16" } } */ + +uint32x4_t +foo1 (uint16x8_t a) +{ + return vmovlbq (a); +} + +/* { dg-final { scan-assembler "vmovlb.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c new file mode 100644 index 00000000000..ef9a6c7a1d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8x16_t a) +{ + return vmovlbq_u8 (a); +} + +/* { dg-final { scan-assembler "vmovlb.u8" } } */ + +uint16x8_t +foo1 (uint8x16_t a) +{ + return vmovlbq (a); +} + +/* { dg-final { scan-assembler "vmovlb.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c new file mode 100644 index 00000000000..3bd5d37fd08 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int16x8_t a) +{ + return vmovltq_s16 (a); +} + +/* { dg-final { scan-assembler "vmovlt.s16" } } */ + +int32x4_t +foo1 (int16x8_t a) +{ + return vmovltq (a); +} + +/* { dg-final { scan-assembler "vmovlt.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c new file mode 100644 index 00000000000..2bd4b7e6ec8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int8x16_t a) +{ + return vmovltq_s8 (a); +} + +/* { dg-final { scan-assembler "vmovlt.s8" } } */ + +int16x8_t +foo1 (int8x16_t a) +{ + return vmovltq (a); +} + +/* { dg-final { scan-assembler "vmovlt.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c new file mode 100644 index 00000000000..65eb459506a --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint16x8_t a) +{ + return vmovltq_u16 (a); +} + +/* { dg-final { scan-assembler "vmovlt.u16" } } */ + +uint32x4_t +foo1 (uint16x8_t a) +{ + return vmovltq (a); +} + +/* { dg-final { scan-assembler "vmovlt.u16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c new file mode 100644 index 00000000000..b4b9f614b5b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint8x16_t a) +{ + return vmovltq_u8 (a); +} + +/* { dg-final { scan-assembler "vmovlt.u8" } } */ + +uint16x8_t +foo1 (uint8x16_t a) +{ + return vmovltq (a); +} + +/* { dg-final { scan-assembler "vmovlt.u8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c new file mode 100644 index 00000000000..faa12585b94 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vmvnq_s16 (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vmvnq (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c new file mode 100644 index 00000000000..739e91972ae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vmvnq_s32 (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vmvnq (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c new file mode 100644 index 00000000000..51f0fbc8e93 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vmvnq_s8 (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vmvnq (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c new file mode 100644 index 00000000000..629d5dfe1e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a) +{ + return vmvnq_u16 (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ + +uint16x8_t +foo1 (uint16x8_t a) +{ + return vmvnq (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c new file mode 100644 index 00000000000..25573b5a83e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint32x4_t +foo (uint32x4_t a) +{ + return vmvnq_u32 (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ + +uint32x4_t +foo1 (uint32x4_t a) +{ + return vmvnq (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c new file mode 100644 index 00000000000..5747d0417d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a) +{ + return vmvnq_u8 (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ + +uint8x16_t +foo1 (uint8x16_t a) +{ + return vmvnq (a); +} + +/* { dg-final { scan-assembler "vmvn" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c new file mode 100644 index 00000000000..75a8deda263 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vnegq_s16 (a); +} + +/* { dg-final { scan-assembler "vneg.s16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vnegq (a); +} + +/* { dg-final { scan-assembler "vneg.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c new file mode 100644 index 00000000000..33c82c7413b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vnegq_s32 (a); +} + +/* { dg-final { scan-assembler "vneg.s32" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vnegq (a); +} + +/* { dg-final { scan-assembler "vneg.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c new file mode 100644 index 00000000000..21655a83239 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vnegq_s8 (a); +} + +/* { dg-final { scan-assembler "vneg.s8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vnegq (a); +} + +/* { dg-final { scan-assembler "vneg.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c new file mode 100644 index 00000000000..2022eadeabc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vqabsq_s16 (a); +} + +/* { dg-final { scan-assembler "vqabs.s16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vqabsq (a); +} + +/* { dg-final { scan-assembler "vqabs.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c new file mode 100644 index 00000000000..a96bb0bd52e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vqabsq_s32 (a); +} + +/* { dg-final { scan-assembler "vqabs.s32" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vqabsq (a); +} + +/* { dg-final { scan-assembler "vqabs.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c new file mode 100644 index 00000000000..7c2c4e6e13e --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqabsq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vqabsq_s8 (a); +} + +/* { dg-final { scan-assembler "vqabs.s8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vqabsq (a); +} + +/* { dg-final { scan-assembler "vqabs.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c new file mode 100644 index 00000000000..f0a8529f3da --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vqnegq_s16 (a); +} + +/* { dg-final { scan-assembler "vqneg.s16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vqnegq (a); +} + +/* { dg-final { scan-assembler "vqneg.s16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c new file mode 100644 index 00000000000..76923a382b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int32x4_t +foo (int32x4_t a) +{ + return vqnegq_s32 (a); +} + +/* { dg-final { scan-assembler "vqneg.s32" } } */ + +int32x4_t +foo1 (int32x4_t a) +{ + return vqnegq (a); +} + +/* { dg-final { scan-assembler "vqneg.s32" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c new file mode 100644 index 00000000000..7bdab5d189b --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vqnegq_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vqnegq_s8 (a); +} + +/* { dg-final { scan-assembler "vqneg.s8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vqnegq (a); +} + +/* { dg-final { scan-assembler "vqneg.s8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c new file mode 100644 index 00000000000..ab62869cae7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vrev16q_s8 (a); +} + +/* { dg-final { scan-assembler "vrev16.8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vrev16q (a); +} + +/* { dg-final { scan-assembler "vrev16.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c new file mode 100644 index 00000000000..ea95db1fa89 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a) +{ + return vrev16q_u8 (a); +} + +/* { dg-final { scan-assembler "vrev16.8" } } */ + +uint8x16_t +foo1 (uint8x16_t a) +{ + return vrev16q (a); +} + +/* { dg-final { scan-assembler "vrev16.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c new file mode 100644 index 00000000000..1b339e74632 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ +/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int16x8_t +foo (int16x8_t a) +{ + return vrev32q_s16 (a); +} + +/* { dg-final { scan-assembler "vrev32.16" } } */ + +int16x8_t +foo1 (int16x8_t a) +{ + return vrev32q (a); +} + +/* { dg-final { scan-assembler "vrev32.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c new file mode 100644 index 00000000000..cb2f8a7e62f --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_s8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +int8x16_t +foo (int8x16_t a) +{ + return vrev32q_s8 (a); +} + +/* { dg-final { scan-assembler "vrev32.8" } } */ + +int8x16_t +foo1 (int8x16_t a) +{ + return vrev32q (a); +} + +/* { dg-final { scan-assembler "vrev32.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c new file mode 100644 index 00000000000..296482c42a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint16x8_t +foo (uint16x8_t a) +{ + return vrev32q_u16 (a); +} + +/* { dg-final { scan-assembler "vrev32.16" } } */ + +uint16x8_t +foo1 (uint16x8_t a) +{ + return vrev32q (a); +} + +/* { dg-final { scan-assembler "vrev32.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c new file mode 100644 index 00000000000..c70b2788647 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +#include "arm_mve.h" + +uint8x16_t +foo (uint8x16_t a) +{ + return vrev32q_u8 (a); +} + +/* { dg-final { scan-assembler "vrev32.8" } } */ + +uint8x16_t +foo1 (uint8x16_t a) +{ + return vrev32q (a); +} + +/* { dg-final { scan-assembler "vrev32.8" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c index 35245ad3693..b2b6bd51985 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s16.c @@ -16,7 +16,7 @@ foo (int16x8_t a) int16x8_t foo1 (int16x8_t a) { - return vrev64q_s16 (a); + return vrev64q (a); } /* { dg-final { scan-assembler "vrev64.16" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c index 2344423cc50..e13f0750a09 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_s32.c @@ -16,7 +16,7 @@ foo (int32x4_t a) int32x4_t foo1 (int32x4_t a) { - return vrev64q_s32 (a); + return vrev64q (a); } /* { dg-final { scan-assembler "vrev64.32" } } */ -- 2.30.2