From 6e0878becfbf211e5bbd141cd3441dfbdb206cc8 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Michel=20D=C3=A4nzer?= Date: Fri, 9 Mar 2007 20:00:13 +0100 Subject: [PATCH] i915tex: Wait for pending scheduled flips before switching vsync pipe. This avoids hangs when the vblank sequence numbers are not in sync between pipes, in particular when they run at different refresh rates. --- src/mesa/drivers/dri/i915tex/intel_buffers.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/src/mesa/drivers/dri/i915tex/intel_buffers.c b/src/mesa/drivers/dri/i915tex/intel_buffers.c index 174f3c6351a..164395719cd 100644 --- a/src/mesa/drivers/dri/i915tex/intel_buffers.c +++ b/src/mesa/drivers/dri/i915tex/intel_buffers.c @@ -300,8 +300,27 @@ intelWindowMoved(struct intel_context *intel) } if (flags != intel_fb->vblank_flags) { + drmVBlank vbl; + int i; + + vbl.request.type = DRM_VBLANK_ABSOLUTE; + + if ( intel_fb->vblank_flags & VBLANK_FLAG_SECONDARY ) { + vbl.request.type |= DRM_VBLANK_SECONDARY; + } + + for (i = 0; i < intel_fb->pf_num_pages; i++) { + vbl.request.sequence = intel_fb->color_rb[i]->vbl_pending; + drmWaitVBlank(intel->driFd, &vbl); + } + intel_fb->vblank_flags = flags; driGetCurrentVBlank(dPriv, intel_fb->vblank_flags, &intel_fb->vbl_seq); + intel_fb->vbl_waited = intel_fb->vbl_seq; + + for (i = 0; i < intel_fb->pf_num_pages; i++) { + intel_fb->color_rb[i]->vbl_pending = intel_fb->vbl_waited; + } } } else { intel_fb->vblank_flags &= ~VBLANK_FLAG_SECONDARY; -- 2.30.2