From 6e17a23b53608872a0c7907c02827d1cf8f79940 Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Tue, 1 Sep 2015 10:32:24 +0000 Subject: [PATCH] [AArch64] Fix FAIL: gcc.target/aarch64/target_attr_crypto_ice_1.c (internal compiler error) * config/aarch64/aarch64.c (aarch64_set_current_function): Re-layout any vector parameters have non-simd layout. * config/aarch64/aarch64-builtins.c (aarch64_relayout_simd_param): Delete. (aarch64_simd_expand_args): Delete call to the above. * gcc.target/aarch64/target_attr_crypto_ice_2.c: New test. From-SVN: r227363 --- gcc/ChangeLog | 8 ++++++ gcc/config/aarch64/aarch64-builtins.c | 25 ------------------- gcc/config/aarch64/aarch64.c | 17 +++++++++++++ gcc/testsuite/ChangeLog | 4 +++ .../aarch64/target_attr_crypto_ice_2.c | 20 +++++++++++++++ 5 files changed, 49 insertions(+), 25 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2e7230b9f9c..401c0c4f453 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2015-09-01 Kyrylo Tkachov + + * config/aarch64/aarch64.c (aarch64_set_current_function): + Re-layout any vector parameters have non-simd layout. + * config/aarch64/aarch64-builtins.c (aarch64_relayout_simd_param): + Delete. + (aarch64_simd_expand_args): Delete call to the above. + 2015-08-31 Mike Frysinger * doc/invoke.texi (asan-stack): Add space before option. diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index 0f4f2b97022..e3a90b5e4dd 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -886,30 +886,6 @@ typedef enum SIMD_ARG_STOP } builtin_simd_arg; -/* Relayout the decl of a function arg. Keep the RTL component the same, - as varasm.c ICEs. It doesn't like reinitializing the RTL - on PARM decls. Something like this needs to be done when compiling a - file without SIMD and then tagging a function with +simd and using SIMD - intrinsics in there. The types will have been laid out assuming no SIMD, - so we want to re-lay them out. */ - -static void -aarch64_relayout_simd_param (tree arg) -{ - tree argdecl = arg; - if (TREE_CODE (argdecl) == SSA_NAME) - argdecl = SSA_NAME_VAR (argdecl); - - if (argdecl - && (TREE_CODE (argdecl) == PARM_DECL - || TREE_CODE (argdecl) == VAR_DECL)) - { - rtx rtl = NULL_RTX; - rtl = DECL_RTL_IF_SET (argdecl); - relayout_decl (argdecl); - SET_DECL_RTL (argdecl, rtl); - } -} static rtx aarch64_simd_expand_args (rtx target, int icode, int have_retval, @@ -940,7 +916,6 @@ aarch64_simd_expand_args (rtx target, int icode, int have_retval, { tree arg = CALL_EXPR_ARG (exp, opc - have_retval); enum machine_mode mode = insn_data[icode].operand[opc].mode; - aarch64_relayout_simd_param (arg); op[opc] = expand_normal (arg); switch (thisarg) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index ce6e1160d10..bc612e47d4f 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -8111,6 +8111,23 @@ aarch64_set_current_function (tree fndecl) = save_target_globals_default_opts (); } } + + if (!fndecl) + return; + + /* If we turned on SIMD make sure that any vector parameters are re-laid out + so that they use proper vector modes. */ + if (TARGET_SIMD) + { + tree parms = DECL_ARGUMENTS (fndecl); + for (; parms && parms != void_list_node; parms = TREE_CHAIN (parms)) + { + if (TREE_CODE (parms) == PARM_DECL + && VECTOR_TYPE_P (TREE_TYPE (parms)) + && DECL_MODE (parms) != TYPE_MODE (TREE_TYPE (parms))) + relayout_decl (parms); + } + } } /* Enum describing the various ways we can handle attributes. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b9d9f84ba74..f14ff330e3f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2015-09-01 Kyrylo Tkachov + + * gcc.target/aarch64/target_attr_crypto_ice_2.c: New test. + 2015-09-01 Paolo Carlini PR c++/61753 diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c new file mode 100644 index 00000000000..d6e7b681832 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=thunderx+nofp" } */ + +/* Make sure that we don't ICE when dealing with vector parameters + in a simd-tagged function within a non-simd translation unit. */ + +#pragma GCC push_options +#pragma GCC target ("+nothing+simd") +typedef unsigned int __uint32_t; +typedef __uint32_t uint32_t ; +typedef __Uint32x4_t uint32x4_t; +#pragma GCC pop_options + + +__attribute__ ((target ("cpu=cortex-a57"))) +uint32x4_t +foo (uint32x4_t a, uint32_t b, uint32x4_t c) +{ + return c; +} -- 2.30.2