From 6e475fefa1fc5e5260169d9b46a33b388aef604d Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 17 Oct 2016 12:42:12 +0200 Subject: [PATCH] radeonsi: merge radeon_llvm_context and si_shader_context MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Nicolai Hähnle Reviewed-by: Emil Velikov Acked-by: Edward O'Callaghan --- src/gallium/drivers/radeonsi/si_shader.c | 464 ++++++++---------- .../drivers/radeonsi/si_shader_internal.h | 89 +++- .../drivers/radeonsi/si_shader_tgsi_alu.c | 2 +- .../drivers/radeonsi/si_shader_tgsi_setup.c | 52 +- 4 files changed, 290 insertions(+), 317 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 194da3194f8..c1300fd6b08 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -58,77 +58,6 @@ struct si_shader_output_values unsigned sid; }; -struct si_shader_context -{ - struct radeon_llvm_context radeon_bld; - struct si_shader *shader; - struct si_screen *screen; - - unsigned type; /* PIPE_SHADER_* specifies the type of shader. */ - bool is_gs_copy_shader; - - /* Whether to generate the optimized shader variant compiled as a whole - * (without a prolog and epilog) - */ - bool is_monolithic; - - int param_streamout_config; - int param_streamout_write_index; - int param_streamout_offset[4]; - int param_vertex_id; - int param_rel_auto_id; - int param_vs_prim_id; - int param_instance_id; - int param_vertex_index0; - int param_tes_u; - int param_tes_v; - int param_tes_rel_patch_id; - int param_tes_patch_id; - int param_es2gs_offset; - int param_oc_lds; - - /* Sets a bit if the dynamic HS control word was 0x80000000. The bit is - * 0x800000 for VS, 0x1 for ES. - */ - int param_tess_offchip; - - LLVMTargetMachineRef tm; - - unsigned invariant_load_md_kind; - unsigned range_md_kind; - unsigned uniform_md_kind; - LLVMValueRef empty_md; - - /* Preloaded descriptors. */ - LLVMValueRef esgs_ring; - LLVMValueRef gsvs_ring[4]; - - LLVMValueRef lds; - LLVMValueRef gs_next_vertex[4]; - LLVMValueRef return_value; - - LLVMTypeRef voidt; - LLVMTypeRef i1; - LLVMTypeRef i8; - LLVMTypeRef i32; - LLVMTypeRef i64; - LLVMTypeRef i128; - LLVMTypeRef f32; - LLVMTypeRef v16i8; - LLVMTypeRef v2i32; - LLVMTypeRef v4i32; - LLVMTypeRef v4f32; - LLVMTypeRef v8i32; - - LLVMValueRef shared_memory; -}; - -static struct si_shader_context *si_shader_context( - struct lp_build_tgsi_context *bld_base) -{ - return (struct si_shader_context *)bld_base; -} - static void si_init_shader_ctx(struct si_shader_context *ctx, struct si_screen *sscreen, struct si_shader *shader, @@ -213,12 +142,12 @@ static LLVMValueRef unpack_param(struct si_shader_context *ctx, unsigned param, unsigned rshift, unsigned bitwidth) { - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; - LLVMValueRef value = LLVMGetParam(ctx->radeon_bld.main_fn, + struct gallivm_state *gallivm = &ctx->gallivm; + LLVMValueRef value = LLVMGetParam(ctx->main_fn, param); if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind) - value = bitcast(&ctx->radeon_bld.soa.bld_base, + value = bitcast(&ctx->soa.bld_base, TGSI_TYPE_UNSIGNED, value); if (rshift) @@ -241,7 +170,7 @@ static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx) return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8); case PIPE_SHADER_TESS_EVAL: - return LLVMGetParam(ctx->radeon_bld.main_fn, + return LLVMGetParam(ctx->main_fn, ctx->param_tes_rel_patch_id); default: @@ -293,7 +222,7 @@ get_tcs_out_patch_stride(struct si_shader_context *ctx) static LLVMValueRef get_tcs_out_patch0_offset(struct si_shader_context *ctx) { - return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld, + return lp_build_mul_imm(&ctx->soa.bld_base.uint_bld, unpack_param(ctx, SI_PARAM_TCS_OUT_OFFSETS, 0, 16), @@ -303,7 +232,7 @@ get_tcs_out_patch0_offset(struct si_shader_context *ctx) static LLVMValueRef get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx) { - return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld, + return lp_build_mul_imm(&ctx->soa.bld_base.uint_bld, unpack_param(ctx, SI_PARAM_TCS_OUT_OFFSETS, 16, 16), @@ -313,7 +242,7 @@ get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx) static LLVMValueRef get_tcs_in_current_patch_offset(struct si_shader_context *ctx) { - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; + struct gallivm_state *gallivm = &ctx->gallivm; LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx); LLVMValueRef rel_patch_id = get_rel_patch_id(ctx); @@ -323,7 +252,7 @@ get_tcs_in_current_patch_offset(struct si_shader_context *ctx) static LLVMValueRef get_tcs_out_current_patch_offset(struct si_shader_context *ctx) { - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; + struct gallivm_state *gallivm = &ctx->gallivm; LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx); LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx); LLVMValueRef rel_patch_id = get_rel_patch_id(ctx); @@ -337,7 +266,7 @@ get_tcs_out_current_patch_offset(struct si_shader_context *ctx) static LLVMValueRef get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx) { - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; + struct gallivm_state *gallivm = &ctx->gallivm; LLVMValueRef patch0_patch_data_offset = get_tcs_out_patch0_patch_data_offset(ctx); LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx); @@ -356,7 +285,7 @@ static LLVMValueRef build_gep0(struct si_shader_context *ctx, LLVMConstInt(ctx->i32, 0, 0), index, }; - return LLVMBuildGEP(ctx->radeon_bld.gallivm.builder, base_ptr, + return LLVMBuildGEP(ctx->gallivm.builder, base_ptr, indices, 2, ""); } @@ -364,7 +293,7 @@ static void build_indexed_store(struct si_shader_context *ctx, LLVMValueRef base_ptr, LLVMValueRef index, LLVMValueRef value) { - struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base; + struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base; struct gallivm_state *gallivm = bld_base->base.gallivm; LLVMBuildStore(gallivm->builder, value, @@ -384,7 +313,7 @@ static LLVMValueRef build_indexed_load(struct si_shader_context *ctx, LLVMValueRef base_ptr, LLVMValueRef index, bool uniform) { - struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base; + struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base; struct gallivm_state *gallivm = bld_base->base.gallivm; LLVMValueRef pointer; @@ -408,7 +337,7 @@ static LLVMValueRef build_indexed_load_const( } static LLVMValueRef get_instance_index_for_fetch( - struct radeon_llvm_context *radeon_bld, + struct si_shader_context *radeon_bld, unsigned param_start_instance, unsigned divisor) { struct si_shader_context *ctx = @@ -428,7 +357,7 @@ static LLVMValueRef get_instance_index_for_fetch( } static void declare_input_vs( - struct radeon_llvm_context *radeon_bld, + struct si_shader_context *radeon_bld, unsigned input_index, const struct tgsi_full_declaration *decl, LLVMValueRef out[4]) @@ -451,7 +380,7 @@ static void declare_input_vs( LLVMValueRef input; /* Load the T list */ - t_list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS); + t_list_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_VERTEX_BUFFERS); t_offset = lp_build_const_int32(gallivm, input_index); @@ -467,12 +396,12 @@ static void declare_input_vs( } else if (divisor) { /* Build index from instance ID, start instance and divisor */ ctx->shader->info.uses_instanceid = true; - buffer_index = get_instance_index_for_fetch(&ctx->radeon_bld, + buffer_index = get_instance_index_for_fetch(ctx, SI_PARAM_START_INSTANCE, divisor); } else { /* Load the buffer index for vertices. */ - LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn, + LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn, ctx->param_vertex_id); LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BASE_VERTEX); @@ -504,16 +433,16 @@ static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base, switch (ctx->type) { case PIPE_SHADER_VERTEX: - return LLVMGetParam(ctx->radeon_bld.main_fn, + return LLVMGetParam(ctx->main_fn, ctx->param_vs_prim_id); case PIPE_SHADER_TESS_CTRL: - return LLVMGetParam(ctx->radeon_bld.main_fn, + return LLVMGetParam(ctx->main_fn, SI_PARAM_PATCH_ID); case PIPE_SHADER_TESS_EVAL: - return LLVMGetParam(ctx->radeon_bld.main_fn, + return LLVMGetParam(ctx->main_fn, ctx->param_tes_patch_id); case PIPE_SHADER_GEOMETRY: - return LLVMGetParam(ctx->radeon_bld.main_fn, + return LLVMGetParam(ctx->main_fn, SI_PARAM_PRIMITIVE_ID); default: assert(0); @@ -529,10 +458,10 @@ static LLVMValueRef get_indirect_index(struct si_shader_context *ctx, const struct tgsi_ind_register *ind, int rel_index) { - struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm; + struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm; LLVMValueRef result; - result = ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle]; + result = ctx->soa.addr[ind->Index][ind->Swizzle]; result = LLVMBuildLoad(gallivm->builder, result, ""); result = LLVMBuildAdd(gallivm->builder, result, lp_build_const_int32(gallivm, rel_index), ""); @@ -556,7 +485,7 @@ static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx, if (HAVE_LLVM <= 0x0308) return LLVMGetUndef(ctx->i32); - return radeon_llvm_bound_index(&ctx->radeon_bld, result, num); + return radeon_llvm_bound_index(ctx, result, num); } @@ -569,7 +498,7 @@ static LLVMValueRef get_dw_address(struct si_shader_context *ctx, LLVMValueRef vertex_dw_stride, LLVMValueRef base_addr) { - struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm; + struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm; struct tgsi_shader_info *info = &ctx->shader->selector->info; ubyte *name, *index, *array_first; int first, param; @@ -667,7 +596,7 @@ static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx, LLVMValueRef vertex_index, LLVMValueRef param_index) { - struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm; + struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm; LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices; LLVMValueRef param_stride, constant16; @@ -711,7 +640,7 @@ static LLVMValueRef get_tcs_tes_buffer_address_from_reg( const struct tgsi_full_dst_register *dst, const struct tgsi_full_src_register *src) { - struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm; + struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm; struct tgsi_shader_info *info = &ctx->shader->selector->info; ubyte *name, *index, *array_first; struct tgsi_full_src_register reg; @@ -787,7 +716,7 @@ static void build_tbuffer_store(struct si_shader_context *ctx, unsigned slc, unsigned tfe) { - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; + struct gallivm_state *gallivm = &ctx->gallivm; LLVMValueRef args[] = { rsrc, vdata, @@ -848,7 +777,7 @@ static LLVMValueRef build_buffer_load(struct si_shader_context *ctx, unsigned glc, unsigned slc) { - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; + struct gallivm_state *gallivm = &ctx->gallivm; unsigned func = CLAMP(num_channels, 1, 3) - 1; if (HAVE_LLVM >= 0x309) { @@ -1057,12 +986,12 @@ static LLVMValueRef fetch_input_tes( struct gallivm_state *gallivm = bld_base->base.gallivm; LLVMValueRef rw_buffers, buffer, base, addr; - rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn, + rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS); buffer = build_indexed_load_const(ctx, rw_buffers, lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP)); - base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds); + base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds); addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg); return buffer_load(bld_base, type, swizzle, buffer, base, addr); @@ -1099,12 +1028,12 @@ static void store_output_tcs(struct lp_build_tgsi_context *bld_base, dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr); } - rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn, + rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS); buffer = build_indexed_load_const(ctx, rw_buffers, lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP)); - base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds); + base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds); buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL); @@ -1143,7 +1072,7 @@ static LLVMValueRef fetch_input_gs( struct lp_build_context *base = &bld_base->base; struct si_shader_context *ctx = si_shader_context(bld_base); struct si_shader *shader = ctx->shader; - struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld; + struct lp_build_context *uint = &ctx->soa.bld_base.uint_bld; struct gallivm_state *gallivm = base->gallivm; LLVMValueRef vtx_offset; LLVMValueRef args[9]; @@ -1179,7 +1108,7 @@ static LLVMValueRef fetch_input_gs( vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2; } vtx_offset = lp_build_mul_imm(uint, - LLVMGetParam(ctx->radeon_bld.main_fn, + LLVMGetParam(ctx->main_fn, vtx_offset_param), 4); @@ -1306,8 +1235,8 @@ static void interp_fs_input(struct si_shader_context *ctx, LLVMValueRef face, LLVMValueRef result[4]) { - struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base; - struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld; + struct lp_build_context *base = &ctx->soa.bld_base.base; + struct lp_build_context *uint = &ctx->soa.bld_base.uint_bld; struct gallivm_state *gallivm = base->gallivm; const char *intr_name; LLVMValueRef attr_number; @@ -1402,8 +1331,8 @@ static void interp_fs_input(struct si_shader_context *ctx, static LLVMValueRef get_interp_param(struct si_shader_context *ctx, int interp_param_idx) { - LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder; - LLVMValueRef main_fn = ctx->radeon_bld.main_fn; + LLVMBuilderRef builder = ctx->gallivm.builder; + LLVMValueRef main_fn = ctx->main_fn; LLVMValueRef param = NULL; /* Handle PRIM_MASK[31] (bc_optimize). */ @@ -1449,7 +1378,7 @@ static LLVMValueRef get_interp_param(struct si_shader_context *ctx, } static void declare_input_fs( - struct radeon_llvm_context *radeon_bld, + struct si_shader_context *radeon_bld, unsigned input_index, const struct tgsi_full_declaration *decl, LLVMValueRef out[4]) @@ -1501,7 +1430,7 @@ static void declare_input_fs( &out[0]); } -static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld) +static LLVMValueRef get_sample_id(struct si_shader_context *radeon_bld) { return unpack_param(si_shader_context(&radeon_bld->soa.bld_base), SI_PARAM_ANCILLARY, 8, 4); @@ -1529,7 +1458,7 @@ static void set_range_metadata(struct si_shader_context *ctx, static LLVMValueRef get_thread_id(struct si_shader_context *ctx) { - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; + struct gallivm_state *gallivm = &ctx->gallivm; LLVMValueRef tid; if (HAVE_LLVM < 0x0308) { @@ -1558,21 +1487,21 @@ static LLVMValueRef buffer_load_const(struct si_shader_context *ctx, LLVMValueRef resource, LLVMValueRef offset) { - LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder; + LLVMBuilderRef builder = ctx->gallivm.builder; LLVMValueRef args[2] = {resource, offset}; return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2, LLVMReadNoneAttribute); } -static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id) +static LLVMValueRef load_sample_position(struct si_shader_context *radeon_bld, LLVMValueRef sample_id) { struct si_shader_context *ctx = si_shader_context(&radeon_bld->soa.bld_base); struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld; struct gallivm_state *gallivm = &radeon_bld->gallivm; LLVMBuilderRef builder = gallivm->builder; - LLVMValueRef desc = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS); + LLVMValueRef desc = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS); LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS); LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index); @@ -1591,7 +1520,7 @@ static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, } static void declare_system_value( - struct radeon_llvm_context *radeon_bld, + struct si_shader_context *radeon_bld, unsigned index, const struct tgsi_full_declaration *decl) { @@ -1723,12 +1652,12 @@ static void declare_system_value( LLVMValueRef rw_buffers, buffer, base, addr; int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0); - rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn, + rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS); buffer = build_indexed_load_const(ctx, rw_buffers, lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP)); - base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds); + base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds); addr = get_tcs_tes_buffer_address(ctx, NULL, lp_build_const_int32(gallivm, param)); @@ -1745,7 +1674,7 @@ static void declare_system_value( int i, offset; slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS); - buf = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS); + buf = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS); buf = build_indexed_load_const(ctx, buf, slot); offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0; @@ -1814,7 +1743,7 @@ static void declare_system_value( radeon_bld->system_values[index] = value; } -static void declare_compute_memory(struct radeon_llvm_context *radeon_bld, +static void declare_compute_memory(struct si_shader_context *radeon_bld, const struct tgsi_full_declaration *decl) { struct si_shader_context *ctx = @@ -1840,7 +1769,7 @@ static void declare_compute_memory(struct radeon_llvm_context *radeon_bld, static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i) { - LLVMValueRef list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, + LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_CONST_BUFFERS); return build_indexed_load_const(ctx, list_ptr, @@ -1874,7 +1803,7 @@ static LLVMValueRef fetch_constant( idx = reg->Register.Index * 4 + swizzle; if (reg->Register.Dimension && reg->Dimension.Indirect) { - LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS); + LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_CONST_BUFFERS); LLVMValueRef index; index = get_bounded_indirect_index(ctx, ®->DimIndirect, reg->Dimension.Index, @@ -1884,7 +1813,7 @@ static LLVMValueRef fetch_constant( bufp = load_const_buffer_desc(ctx, buf); if (reg->Register.Indirect) { - addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle]; + addr = ctx->soa.addr[ireg->Index][ireg->Swizzle]; addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg"); addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16); addr = lp_build_add(&bld_base->uint_bld, addr, @@ -1940,7 +1869,7 @@ static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base, { struct si_shader_context *ctx = si_shader_context(bld_base); struct lp_build_context *uint = - &ctx->radeon_bld.soa.bld_base.uint_bld; + &ctx->soa.bld_base.uint_bld; struct lp_build_context *base = &bld_base->base; struct gallivm_state *gallivm = base->gallivm; LLVMBuilderRef builder = base->gallivm->builder; @@ -2122,7 +2051,7 @@ static void si_alpha_test(struct lp_build_tgsi_context *bld_base, struct gallivm_state *gallivm = bld_base->base.gallivm; if (ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER) { - LLVMValueRef alpha_ref = LLVMGetParam(ctx->radeon_bld.main_fn, + LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn, SI_PARAM_ALPHA_REF); LLVMValueRef alpha_pass = @@ -2152,7 +2081,7 @@ static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context * LLVMValueRef coverage; /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */ - coverage = LLVMGetParam(ctx->radeon_bld.main_fn, + coverage = LLVMGetParam(ctx->main_fn, samplemask_param); coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage); @@ -2175,12 +2104,12 @@ static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base, { struct si_shader_context *ctx = si_shader_context(bld_base); struct lp_build_context *base = &bld_base->base; - struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld; + struct lp_build_context *uint = &ctx->soa.bld_base.uint_bld; unsigned reg_index; unsigned chan; unsigned const_chan; LLVMValueRef base_elt; - LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS); + LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS); LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_VS_CONST_CLIP_PLANES); LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index); @@ -2245,12 +2174,12 @@ static void si_llvm_emit_streamout(struct si_shader_context *ctx, unsigned noutput) { struct pipe_stream_output_info *so = &ctx->shader->selector->so; - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; + struct gallivm_state *gallivm = &ctx->gallivm; LLVMBuilderRef builder = gallivm->builder; int i, j; struct lp_build_if_state if_ctx; LLVMValueRef so_buffers[4]; - LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, + LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS); /* Load the descriptors. */ @@ -2288,7 +2217,7 @@ static void si_llvm_emit_streamout(struct si_shader_context *ctx, */ LLVMValueRef so_write_index = - LLVMGetParam(ctx->radeon_bld.main_fn, + LLVMGetParam(ctx->main_fn, ctx->param_streamout_write_index); /* Compute (streamout_write_index + thread_id). */ @@ -2300,7 +2229,7 @@ static void si_llvm_emit_streamout(struct si_shader_context *ctx, if (!so->stride[i]) continue; - LLVMValueRef so_offset = LLVMGetParam(ctx->radeon_bld.main_fn, + LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn, ctx->param_streamout_offset[i]); so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), ""); @@ -2378,7 +2307,7 @@ static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base, struct si_shader *shader = ctx->shader; struct lp_build_context *base = &bld_base->base; struct lp_build_context *uint = - &ctx->radeon_bld.soa.bld_base.uint_bld; + &ctx->soa.bld_base.uint_bld; LLVMValueRef args[9]; LLVMValueRef pos_args[4][9] = { { 0 } }; LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL; @@ -2554,11 +2483,11 @@ static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base) invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5); - rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS); + rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS); buffer = build_indexed_load_const(ctx, rw_buffers, lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP)); - buffer_offset = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds); + buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds); lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8); lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id, @@ -2661,13 +2590,13 @@ static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base, vec1 = lp_build_gather_values(gallivm, out+4, stride - 4); /* Get the buffer. */ - rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn, + rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS); buffer = build_indexed_load_const(ctx, rw_buffers, lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR)); /* Get the offset. */ - tf_base = LLVMGetParam(ctx->radeon_bld.main_fn, + tf_base = LLVMGetParam(ctx->main_fn, SI_PARAM_TESS_FACTOR_OFFSET); byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id, lp_build_const_int32(gallivm, 4 * stride), ""); @@ -2710,7 +2639,7 @@ static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base) unsigned vgpr; /* RW_BUFFERS pointer */ - rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn, + rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS); rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, ""); rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, ""); @@ -2722,7 +2651,7 @@ static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base) ret = LLVMBuildInsertValue(builder, ret, rw1, 1, ""); /* Tess factor buffer soffset is after user SGPRs. */ - tf_soffset = LLVMGetParam(ctx->radeon_bld.main_fn, + tf_soffset = LLVMGetParam(ctx->main_fn, SI_PARAM_TESS_FACTOR_OFFSET); ret = LLVMBuildInsertValue(builder, ret, tf_soffset, SI_TCS_NUM_USER_SGPR + 1, ""); @@ -2751,7 +2680,7 @@ static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base) struct tgsi_shader_info *info = &shader->selector->info; struct gallivm_state *gallivm = bld_base->base.gallivm; unsigned i, chan; - LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn, + LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn, ctx->param_rel_auto_id); LLVMValueRef vertex_dw_stride = unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8); @@ -2761,7 +2690,7 @@ static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base) /* Write outputs to LDS. The next shader (TCS aka HS) will read * its inputs from it. */ for (i = 0; i < info->num_outputs; i++) { - LLVMValueRef *out_ptr = ctx->radeon_bld.soa.outputs[i]; + LLVMValueRef *out_ptr = ctx->soa.outputs[i]; unsigned name = info->output_semantic_name[i]; unsigned index = info->output_semantic_index[i]; int param = si_shader_io_get_unique_index(name, index); @@ -2781,14 +2710,14 @@ static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base) struct gallivm_state *gallivm = bld_base->base.gallivm; struct si_shader *es = ctx->shader; struct tgsi_shader_info *info = &es->selector->info; - LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn, + LLVMValueRef soffset = LLVMGetParam(ctx->main_fn, ctx->param_es2gs_offset); unsigned chan; int i; for (i = 0; i < info->num_outputs; i++) { LLVMValueRef *out_ptr = - ctx->radeon_bld.soa.outputs[i]; + ctx->soa.outputs[i]; int param_index; if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX || @@ -2821,7 +2750,7 @@ static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base) LLVMValueRef args[2]; args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE); - args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID); + args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID); lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg", ctx->voidt, args, 2, 0); } @@ -2857,7 +2786,7 @@ static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base) /* We've found a color. */ if (!cond) { /* The state is in the first bit of the user SGPR. */ - cond = LLVMGetParam(ctx->radeon_bld.main_fn, + cond = LLVMGetParam(ctx->main_fn, SI_PARAM_VS_STATE_BITS); cond = LLVMBuildTrunc(gallivm->builder, cond, ctx->i1, ""); @@ -2865,7 +2794,7 @@ static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base) } for (j = 0; j < 4; j++) { - addr = ctx->radeon_bld.soa.outputs[i][j]; + addr = ctx->soa.outputs[i][j]; val = LLVMBuildLoad(gallivm->builder, addr, ""); val = radeon_llvm_saturate(bld_base, val); LLVMBuildStore(gallivm->builder, val, addr); @@ -2883,7 +2812,7 @@ static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base) for (j = 0; j < 4; j++) outputs[i].values[j] = LLVMBuildLoad(gallivm->builder, - ctx->radeon_bld.soa.outputs[i][j], + ctx->soa.outputs[i][j], ""); } @@ -3079,7 +3008,7 @@ static void si_emit_ps_exports(struct si_shader_context *ctx, struct si_ps_exports *exp) { for (unsigned i = 0; i < exp->num; i++) - lp_build_intrinsic(ctx->radeon_bld.gallivm.builder, + lp_build_intrinsic(ctx->gallivm.builder, "llvm.SI.export", ctx->voidt, exp->args[i], 9, 0); } @@ -3165,20 +3094,20 @@ static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base) switch (semantic_name) { case TGSI_SEMANTIC_POSITION: depth = LLVMBuildLoad(builder, - ctx->radeon_bld.soa.outputs[i][2], ""); + ctx->soa.outputs[i][2], ""); break; case TGSI_SEMANTIC_STENCIL: stencil = LLVMBuildLoad(builder, - ctx->radeon_bld.soa.outputs[i][1], ""); + ctx->soa.outputs[i][1], ""); break; case TGSI_SEMANTIC_SAMPLEMASK: samplemask = LLVMBuildLoad(builder, - ctx->radeon_bld.soa.outputs[i][0], ""); + ctx->soa.outputs[i][0], ""); break; case TGSI_SEMANTIC_COLOR: for (j = 0; j < 4; j++) color[j] = LLVMBuildLoad(builder, - ctx->radeon_bld.soa.outputs[i][j], ""); + ctx->soa.outputs[i][j], ""); si_export_mrt_color(bld_base, color, semantic_index, SI_PARAM_SAMPLE_COVERAGE, @@ -3232,22 +3161,22 @@ static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base) case TGSI_SEMANTIC_COLOR: assert(semantic_index < 8); for (j = 0; j < 4; j++) { - LLVMValueRef ptr = ctx->radeon_bld.soa.outputs[i][j]; + LLVMValueRef ptr = ctx->soa.outputs[i][j]; LLVMValueRef result = LLVMBuildLoad(builder, ptr, ""); color[semantic_index][j] = result; } break; case TGSI_SEMANTIC_POSITION: depth = LLVMBuildLoad(builder, - ctx->radeon_bld.soa.outputs[i][2], ""); + ctx->soa.outputs[i][2], ""); break; case TGSI_SEMANTIC_STENCIL: stencil = LLVMBuildLoad(builder, - ctx->radeon_bld.soa.outputs[i][1], ""); + ctx->soa.outputs[i][1], ""); break; case TGSI_SEMANTIC_SAMPLEMASK: samplemask = LLVMBuildLoad(builder, - ctx->radeon_bld.soa.outputs[i][0], ""); + ctx->soa.outputs[i][0], ""); break; default: fprintf(stderr, "Warning: SI unhandled fs output type:%d\n", @@ -3261,7 +3190,7 @@ static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base) /* Set SGPRs. */ ret = LLVMBuildInsertValue(builder, ret, bitcast(bld_base, TGSI_TYPE_SIGNED, - LLVMGetParam(ctx->radeon_bld.main_fn, + LLVMGetParam(ctx->main_fn, SI_PARAM_ALPHA_REF)), SI_SGPR_ALPHA_REF, ""); @@ -3285,7 +3214,7 @@ static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base) if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC) vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC; ret = LLVMBuildInsertValue(builder, ret, - LLVMGetParam(ctx->radeon_bld.main_fn, + LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE), vgpr++, ""); ctx->return_value = ret; @@ -3374,7 +3303,7 @@ static void build_tex_intrinsic(const struct lp_build_tgsi_action *action, */ static void emit_optimization_barrier(struct si_shader_context *ctx) { - LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder; + LLVMBuilderRef builder = ctx->gallivm.builder; LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false); LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false); LLVMBuildCall(builder, inlineasm, NULL, 0, ""); @@ -3382,7 +3311,7 @@ static void emit_optimization_barrier(struct si_shader_context *ctx) static void emit_waitcnt(struct si_shader_context *ctx) { - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; + struct gallivm_state *gallivm = &ctx->gallivm; LLVMBuilderRef builder = gallivm->builder; LLVMValueRef args[1] = { lp_build_const_int32(gallivm, 0xf70) @@ -3406,7 +3335,7 @@ shader_buffer_fetch_rsrc(struct si_shader_context *ctx, const struct tgsi_full_src_register *reg) { LLVMValueRef index; - LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, + LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_SHADER_BUFFERS); if (!reg->Register.Indirect) @@ -3457,7 +3386,7 @@ static LLVMValueRef force_dcc_off(struct si_shader_context *ctx, if (ctx->screen->b.chip_class <= CIK) { return rsrc; } else { - LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder; + LLVMBuilderRef builder = ctx->gallivm.builder; LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0); LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0); LLVMValueRef tmp; @@ -3479,7 +3408,7 @@ image_fetch_rsrc( LLVMValueRef *rsrc) { struct si_shader_context *ctx = si_shader_context(bld_base); - LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, + LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_IMAGES); LLVMValueRef index, tmp; @@ -3590,8 +3519,8 @@ static LLVMValueRef extract_rsrc_top_half( struct si_shader_context *ctx, LLVMValueRef rsrc) { - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; - struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base; + struct gallivm_state *gallivm = &ctx->gallivm; + struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base; LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2); rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, ""); @@ -3680,7 +3609,7 @@ static void load_emit_buffer(struct si_shader_context *ctx, struct lp_build_emit_data *emit_data) { const struct tgsi_full_instruction *inst = emit_data->inst; - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; + struct gallivm_state *gallivm = &ctx->gallivm; LLVMBuilderRef builder = gallivm->builder; uint writemask = inst->Dst[0].Register.WriteMask; uint count = util_last_bit(writemask); @@ -3712,12 +3641,12 @@ static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx, const struct tgsi_full_instruction *inst, LLVMTypeRef type, int arg) { - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; + struct gallivm_state *gallivm = &ctx->gallivm; LLVMBuilderRef builder = gallivm->builder; LLVMValueRef offset, ptr; int addr_space; - offset = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, arg, 0); + offset = lp_build_emit_fetch(&ctx->soa.bld_base, inst, arg, 0); offset = LLVMBuildBitCast(builder, offset, ctx->i32, ""); ptr = ctx->shared_memory; @@ -3733,8 +3662,8 @@ static void load_emit_memory( struct lp_build_emit_data *emit_data) { const struct tgsi_full_instruction *inst = emit_data->inst; - struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base; - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; + struct lp_build_context *base = &ctx->soa.bld_base.base; + struct gallivm_state *gallivm = &ctx->gallivm; LLVMBuilderRef builder = gallivm->builder; unsigned writemask = inst->Dst[0].Register.WriteMask; LLVMValueRef channels[4], ptr, derived_ptr, index; @@ -3890,9 +3819,9 @@ static void store_emit_buffer( struct lp_build_emit_data *emit_data) { const struct tgsi_full_instruction *inst = emit_data->inst; - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; + struct gallivm_state *gallivm = &ctx->gallivm; LLVMBuilderRef builder = gallivm->builder; - struct lp_build_context *uint_bld = &ctx->radeon_bld.soa.bld_base.uint_bld; + struct lp_build_context *uint_bld = &ctx->soa.bld_base.uint_bld; LLVMValueRef base_data = emit_data->args[0]; LLVMValueRef base_offset = emit_data->args[3]; unsigned writemask = inst->Dst[0].Register.WriteMask; @@ -3962,8 +3891,8 @@ static void store_emit_memory( struct lp_build_emit_data *emit_data) { const struct tgsi_full_instruction *inst = emit_data->inst; - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; - struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base; + struct gallivm_state *gallivm = &ctx->gallivm; + struct lp_build_context *base = &ctx->soa.bld_base.base; LLVMBuilderRef builder = gallivm->builder; unsigned writemask = inst->Dst[0].Register.WriteMask; LLVMValueRef ptr, derived_ptr, data, index; @@ -3975,7 +3904,7 @@ static void store_emit_memory( if (!(writemask & (1 << chan))) { continue; } - data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 1, chan); + data = lp_build_emit_fetch(&ctx->soa.bld_base, inst, 1, chan); index = lp_build_const_int32(gallivm, chan); derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, ""); LLVMBuildStore(builder, data, derived_ptr); @@ -4088,19 +4017,19 @@ static void atomic_fetch_args( static void atomic_emit_memory(struct si_shader_context *ctx, struct lp_build_emit_data *emit_data) { - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; + struct gallivm_state *gallivm = &ctx->gallivm; LLVMBuilderRef builder = gallivm->builder; const struct tgsi_full_instruction * inst = emit_data->inst; LLVMValueRef ptr, result, arg; ptr = get_memory_ptr(ctx, inst, ctx->i32, 1); - arg = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 2, 0); + arg = lp_build_emit_fetch(&ctx->soa.bld_base, inst, 2, 0); arg = LLVMBuildBitCast(builder, arg, ctx->i32, ""); if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) { LLVMValueRef new_data; - new_data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, + new_data = lp_build_emit_fetch(&ctx->soa.bld_base, inst, 3, 0); new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, ""); @@ -4273,7 +4202,7 @@ static void set_tex_fetch_args(struct si_shader_context *ctx, LLVMValueRef *param, unsigned count, unsigned dmask) { - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; + struct gallivm_state *gallivm = &ctx->gallivm; unsigned num_args; unsigned is_rect = target == TGSI_TEXTURE_RECT; @@ -4333,7 +4262,7 @@ static LLVMValueRef load_sampler_desc_custom(struct si_shader_context *ctx, LLVMValueRef list, LLVMValueRef index, enum desc_type type) { - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; + struct gallivm_state *gallivm = &ctx->gallivm; LLVMBuilderRef builder = gallivm->builder; switch (type) { @@ -4361,7 +4290,7 @@ static LLVMValueRef load_sampler_desc_custom(struct si_shader_context *ctx, static LLVMValueRef load_sampler_desc(struct si_shader_context *ctx, LLVMValueRef index, enum desc_type type) { - LLVMValueRef list = LLVMGetParam(ctx->radeon_bld.main_fn, + LLVMValueRef list = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLERS); return load_sampler_desc_custom(ctx, list, index, type); @@ -4381,7 +4310,7 @@ static LLVMValueRef load_sampler_desc(struct si_shader_context *ctx, static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx, LLVMValueRef res, LLVMValueRef samp) { - LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder; + LLVMBuilderRef builder = ctx->gallivm.builder; LLVMValueRef img7, samp0; if (ctx->screen->b.chip_class >= VI) @@ -4850,7 +4779,7 @@ static void si_lower_gather4_integer(struct si_shader_context *ctx, const char *intr_name, unsigned coord_vgpr_index) { - LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder; + LLVMBuilderRef builder = ctx->gallivm.builder; LLVMValueRef coord = emit_data->args[0]; LLVMValueRef half_texel[2]; int c; @@ -4869,9 +4798,9 @@ static void si_lower_gather4_integer(struct si_shader_context *ctx, set_tex_fetch_args(ctx, &txq_emit_data, TGSI_OPCODE_TXQ, txq_inst.Texture.Texture, emit_data->args[1], NULL, - &ctx->radeon_bld.soa.bld_base.uint_bld.zero, + &ctx->soa.bld_base.uint_bld.zero, 1, 0xf); - txq_emit(NULL, &ctx->radeon_bld.soa.bld_base, &txq_emit_data); + txq_emit(NULL, &ctx->soa.bld_base, &txq_emit_data); /* Compute -0.5 / size. */ for (c = 0; c < 2; c++) { @@ -4880,7 +4809,7 @@ static void si_lower_gather4_integer(struct si_shader_context *ctx, LLVMConstInt(ctx->i32, c, 0), ""); half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, ""); half_texel[c] = - lp_build_emit_llvm_unary(&ctx->radeon_bld.soa.bld_base, + lp_build_emit_llvm_unary(&ctx->soa.bld_base, TGSI_OPCODE_RCP, half_texel[c]); half_texel[c] = LLVMBuildFMul(builder, half_texel[c], LLVMConstReal(ctx->f32, -0.5), ""); @@ -5180,7 +5109,7 @@ static void interp_fetch_args( emit_data->inst, 1, TGSI_CHAN_X); sample_id = LLVMBuildBitCast(gallivm->builder, sample_id, ctx->i32, ""); - sample_position = load_sample_position(&ctx->radeon_bld, sample_id); + sample_position = load_sample_position(ctx, sample_id); emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder, sample_position, @@ -5209,7 +5138,7 @@ static void build_interp_intrinsic(const struct lp_build_tgsi_action *action, int chan; int i; LLVMValueRef attr_number; - LLVMValueRef params = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK); + LLVMValueRef params = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK); int interp_param_idx; unsigned interp = shader->selector->info.input_interpolate[input_index]; unsigned location; @@ -5318,7 +5247,7 @@ static void si_llvm_emit_vertex( struct si_shader *shader = ctx->shader; struct tgsi_shader_info *info = &shader->selector->info; struct gallivm_state *gallivm = bld_base->base.gallivm; - LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn, + LLVMValueRef soffset = LLVMGetParam(ctx->main_fn, SI_PARAM_GS2VS_OFFSET); LLVMValueRef gs_next_vertex; LLVMValueRef can_emit, kill; @@ -5351,7 +5280,7 @@ static void si_llvm_emit_vertex( for (i = 0; i < info->num_outputs; i++) { LLVMValueRef *out_ptr = - ctx->radeon_bld.soa.outputs[i]; + ctx->soa.outputs[i]; for (chan = 0; chan < 4; chan++) { LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""); @@ -5380,7 +5309,7 @@ static void si_llvm_emit_vertex( /* Signal vertex emission */ args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8)); - args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID); + args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID); lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg", ctx->voidt, args, 2, 0); } @@ -5399,7 +5328,7 @@ static void si_llvm_emit_primitive( /* Signal primitive cut */ stream = si_llvm_get_stream(bld_base, emit_data); args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8)); - args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID); + args[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID); lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg", ctx->voidt, args, 2, 0); } @@ -5442,13 +5371,13 @@ static void si_create_function(struct si_shader_context *ctx, { int i; - radeon_llvm_create_func(&ctx->radeon_bld, returns, num_returns, + radeon_llvm_create_func(ctx, returns, num_returns, params, num_params); - radeon_llvm_shader_type(ctx->radeon_bld.main_fn, ctx->type); - ctx->return_value = LLVMGetUndef(ctx->radeon_bld.return_type); + radeon_llvm_shader_type(ctx->main_fn, ctx->type); + ctx->return_value = LLVMGetUndef(ctx->return_type); for (i = 0; i <= last_sgpr; ++i) { - LLVMValueRef P = LLVMGetParam(ctx->radeon_bld.main_fn, i); + LLVMValueRef P = LLVMGetParam(ctx->main_fn, i); /* The combination of: * - ByVal @@ -5466,16 +5395,16 @@ static void si_create_function(struct si_shader_context *ctx, if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) { /* These were copied from some LLVM test. */ - LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn, + LLVMAddTargetDependentFunctionAttr(ctx->main_fn, "less-precise-fpmad", "true"); - LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn, + LLVMAddTargetDependentFunctionAttr(ctx->main_fn, "no-infs-fp-math", "true"); - LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn, + LLVMAddTargetDependentFunctionAttr(ctx->main_fn, "no-nans-fp-math", "true"); - LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn, + LLVMAddTargetDependentFunctionAttr(ctx->main_fn, "unsafe-fp-math", "true"); } @@ -5483,7 +5412,7 @@ static void si_create_function(struct si_shader_context *ctx, static void create_meta_data(struct si_shader_context *ctx) { - struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm; + struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm; ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(gallivm->context, "invariant.load", 14); @@ -5542,8 +5471,8 @@ static unsigned llvm_get_type_size(LLVMTypeRef type) static void declare_tess_lds(struct si_shader_context *ctx) { - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; - struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base; + struct gallivm_state *gallivm = &ctx->gallivm; + struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base; struct lp_build_context *uint = &bld_base->uint_bld; unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768; @@ -5554,7 +5483,7 @@ static void declare_tess_lds(struct si_shader_context *ctx) static void create_function(struct si_shader_context *ctx) { - struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base; + struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base; struct gallivm_state *gallivm = bld_base->base.gallivm; struct si_shader *shader = ctx->shader; LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32; @@ -5766,7 +5695,7 @@ static void create_function(struct si_shader_context *ctx) /* Reserve register locations for VGPR inputs the PS prolog may need. */ if (ctx->type == PIPE_SHADER_FRAGMENT && !ctx->is_monolithic) { - radeon_llvm_add_attribute(ctx->radeon_bld.main_fn, + radeon_llvm_add_attribute(ctx->main_fn, "InitialPSInputAddr", S_0286D0_PERSP_SAMPLE_ENA(1) | S_0286D0_PERSP_CENTER_ENA(1) | @@ -5790,7 +5719,7 @@ static void create_function(struct si_shader_context *ctx) max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK; } - radeon_llvm_add_attribute(ctx->radeon_bld.main_fn, + radeon_llvm_add_attribute(ctx->main_fn, "amdgpu-max-work-group-size", max_work_group_size); } @@ -5835,9 +5764,9 @@ static void create_function(struct si_shader_context *ctx) static void preload_ring_buffers(struct si_shader_context *ctx) { struct gallivm_state *gallivm = - ctx->radeon_bld.soa.bld_base.base.gallivm; + ctx->soa.bld_base.base.gallivm; - LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, + LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS); if ((ctx->type == PIPE_SHADER_VERTEX && @@ -5876,7 +5805,7 @@ static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx, unsigned param_pos_fixed_pt) { struct lp_build_tgsi_context *bld_base = - &ctx->radeon_bld.soa.bld_base; + &ctx->soa.bld_base; struct gallivm_state *gallivm = bld_base->base.gallivm; LLVMBuilderRef builder = gallivm->builder; LLVMValueRef slot, desc, offset, row, bit, address[2]; @@ -6345,9 +6274,9 @@ int si_compile_llvm(struct si_screen *sscreen, static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret) { if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind) - LLVMBuildRetVoid(ctx->radeon_bld.gallivm.builder); + LLVMBuildRetVoid(ctx->gallivm.builder); else - LLVMBuildRet(ctx->radeon_bld.gallivm.builder, ret); + LLVMBuildRet(ctx->gallivm.builder, ret); } /* Generate code for the hardware VS shader stage to go with a geometry shader */ @@ -6356,8 +6285,8 @@ static int si_generate_gs_copy_shader(struct si_screen *sscreen, struct si_shader *gs, struct pipe_debug_callback *debug) { - struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; - struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base; + struct gallivm_state *gallivm = &ctx->gallivm; + struct lp_build_tgsi_context *bld_base = &ctx->soa.bld_base; struct lp_build_context *uint = &bld_base->uint_bld; struct si_shader_output_values *outputs; struct tgsi_shader_info *gsinfo = &gs->selector->info; @@ -6376,7 +6305,7 @@ static int si_generate_gs_copy_shader(struct si_screen *sscreen, args[0] = ctx->gsvs_ring[0]; args[1] = lp_build_mul_imm(uint, - LLVMGetParam(ctx->radeon_bld.main_fn, + LLVMGetParam(ctx->main_fn, ctx->param_vertex_id), 4); args[3] = uint->zero; @@ -6417,8 +6346,7 @@ static int si_generate_gs_copy_shader(struct si_screen *sscreen, r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY)) LLVMDumpModule(bld_base->base.gallivm->module); - radeon_llvm_finalize_module( - &ctx->radeon_bld, + radeon_llvm_finalize_module(ctx, r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_GEOMETRY)); r = si_compile_llvm(sscreen, &ctx->shader->binary, @@ -6434,7 +6362,7 @@ static int si_generate_gs_copy_shader(struct si_screen *sscreen, r = si_shader_binary_upload(sscreen, ctx->shader); } - radeon_llvm_dispose(&ctx->radeon_bld); + radeon_llvm_dispose(ctx); FREE(outputs); return r; @@ -6506,10 +6434,10 @@ static void si_init_shader_ctx(struct si_shader_context *ctx, memset(ctx, 0, sizeof(*ctx)); radeon_llvm_context_init( - &ctx->radeon_bld, "amdgcn--", + ctx, "amdgcn--", (shader && shader->selector) ? &shader->selector->info : NULL, (shader && shader->selector) ? shader->selector->tokens : NULL); - si_shader_context_init_alu(&ctx->radeon_bld.soa.bld_base); + si_shader_context_init_alu(&ctx->soa.bld_base); ctx->tm = tm; ctx->screen = sscreen; if (shader && shader->selector) @@ -6518,20 +6446,20 @@ static void si_init_shader_ctx(struct si_shader_context *ctx, ctx->type = -1; ctx->shader = shader; - ctx->voidt = LLVMVoidTypeInContext(ctx->radeon_bld.gallivm.context); - ctx->i1 = LLVMInt1TypeInContext(ctx->radeon_bld.gallivm.context); - ctx->i8 = LLVMInt8TypeInContext(ctx->radeon_bld.gallivm.context); - ctx->i32 = LLVMInt32TypeInContext(ctx->radeon_bld.gallivm.context); - ctx->i64 = LLVMInt64TypeInContext(ctx->radeon_bld.gallivm.context); - ctx->i128 = LLVMIntTypeInContext(ctx->radeon_bld.gallivm.context, 128); - ctx->f32 = LLVMFloatTypeInContext(ctx->radeon_bld.gallivm.context); + ctx->voidt = LLVMVoidTypeInContext(ctx->gallivm.context); + ctx->i1 = LLVMInt1TypeInContext(ctx->gallivm.context); + ctx->i8 = LLVMInt8TypeInContext(ctx->gallivm.context); + ctx->i32 = LLVMInt32TypeInContext(ctx->gallivm.context); + ctx->i64 = LLVMInt64TypeInContext(ctx->gallivm.context); + ctx->i128 = LLVMIntTypeInContext(ctx->gallivm.context, 128); + ctx->f32 = LLVMFloatTypeInContext(ctx->gallivm.context); ctx->v16i8 = LLVMVectorType(ctx->i8, 16); ctx->v2i32 = LLVMVectorType(ctx->i32, 2); ctx->v4i32 = LLVMVectorType(ctx->i32, 4); ctx->v4f32 = LLVMVectorType(ctx->f32, 4); ctx->v8i32 = LLVMVectorType(ctx->i32, 8); - bld_base = &ctx->radeon_bld.soa.bld_base; + bld_base = &ctx->soa.bld_base; bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant; bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action; @@ -6620,12 +6548,12 @@ int si_compile_tgsi_shader(struct si_screen *sscreen, shader->info.uses_instanceid = sel->info.uses_instanceid; - bld_base = &ctx.radeon_bld.soa.bld_base; - ctx.radeon_bld.load_system_value = declare_system_value; + bld_base = &ctx.soa.bld_base; + ctx.load_system_value = declare_system_value; switch (ctx.type) { case PIPE_SHADER_VERTEX: - ctx.radeon_bld.load_input = declare_input_vs; + ctx.load_input = declare_input_vs; if (shader->key.vs.as_ls) bld_base->emit_epilogue = si_llvm_emit_ls_epilogue; else if (shader->key.vs.as_es) @@ -6651,14 +6579,14 @@ int si_compile_tgsi_shader(struct si_screen *sscreen, bld_base->emit_epilogue = si_llvm_emit_gs_epilogue; break; case PIPE_SHADER_FRAGMENT: - ctx.radeon_bld.load_input = declare_input_fs; + ctx.load_input = declare_input_fs; if (is_monolithic) bld_base->emit_epilogue = si_llvm_emit_fs_epilogue; else bld_base->emit_epilogue = si_llvm_return_fs_outputs; break; case PIPE_SHADER_COMPUTE: - ctx.radeon_bld.declare_memory_region = declare_compute_memory; + ctx.declare_memory_region = declare_compute_memory; break; default: assert(!"Unsupported shader type"); @@ -6671,7 +6599,7 @@ int si_compile_tgsi_shader(struct si_screen *sscreen, if (ctx.is_monolithic && sel->type == PIPE_SHADER_FRAGMENT && shader->key.ps.prolog.poly_stipple) { - LLVMValueRef list = LLVMGetParam(ctx.radeon_bld.main_fn, + LLVMValueRef list = LLVMGetParam(ctx.main_fn, SI_PARAM_RW_BUFFERS); si_llvm_emit_polygon_stipple(&ctx, list, SI_PARAM_POS_FIXED_PT); @@ -6699,9 +6627,8 @@ int si_compile_tgsi_shader(struct si_screen *sscreen, r600_can_dump_shader(&sscreen->b, ctx.type)) LLVMDumpModule(mod); - radeon_llvm_finalize_module( - &ctx.radeon_bld, - r600_extra_shader_checks(&sscreen->b, ctx.type)); + radeon_llvm_finalize_module(&ctx, + r600_extra_shader_checks(&sscreen->b, ctx.type)); r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm, mod, debug, ctx.type, "TGSI shader"); @@ -6710,7 +6637,7 @@ int si_compile_tgsi_shader(struct si_screen *sscreen, goto out; } - radeon_llvm_dispose(&ctx.radeon_bld); + radeon_llvm_dispose(&ctx); /* Validate SGPR and VGPR usage for compute to detect compiler bugs. * LLVM 3.9svn has this bug. @@ -6886,7 +6813,7 @@ static bool si_compile_vs_prolog(struct si_screen *sscreen, union si_shader_part_key *key = &out->key; struct si_shader shader = {}; struct si_shader_context ctx; - struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm; + struct gallivm_state *gallivm = &ctx.gallivm; LLVMTypeRef *params, *returns; LLVMValueRef ret, func; int last_sgpr, num_params, num_returns, i; @@ -6927,7 +6854,7 @@ static bool si_compile_vs_prolog(struct si_screen *sscreen, /* Create the function. */ si_create_function(&ctx, returns, num_returns, params, num_params, last_sgpr); - func = ctx.radeon_bld.main_fn; + func = ctx.main_fn; /* Copy inputs to outputs. This should be no-op, as the registers match, * but it will prevent the compiler from overwriting them unintentionally. @@ -6950,7 +6877,7 @@ static bool si_compile_vs_prolog(struct si_screen *sscreen, if (divisor) { /* InstanceID / Divisor + StartInstance */ - index = get_instance_index_for_fetch(&ctx.radeon_bld, + index = get_instance_index_for_fetch(&ctx, SI_SGPR_START_INSTANCE, divisor); } else { @@ -6967,8 +6894,7 @@ static bool si_compile_vs_prolog(struct si_screen *sscreen, /* Compile. */ si_llvm_build_ret(&ctx, ret); - radeon_llvm_finalize_module( - &ctx.radeon_bld, + radeon_llvm_finalize_module(&ctx, r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_VERTEX)); if (si_compile_llvm(sscreen, &out->binary, &out->config, tm, @@ -6976,7 +6902,7 @@ static bool si_compile_vs_prolog(struct si_screen *sscreen, "Vertex Shader Prolog")) status = false; - radeon_llvm_dispose(&ctx.radeon_bld); + radeon_llvm_dispose(&ctx); return status; } @@ -6996,8 +6922,8 @@ static bool si_compile_vs_epilog(struct si_screen *sscreen, { union si_shader_part_key *key = &out->key; struct si_shader_context ctx; - struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm; - struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base; + struct gallivm_state *gallivm = &ctx.gallivm; + struct lp_build_tgsi_context *bld_base = &ctx.soa.bld_base; LLVMTypeRef params[5]; int num_params, i; bool status = true; @@ -7028,7 +6954,7 @@ static bool si_compile_vs_epilog(struct si_screen *sscreen, args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM + key->vs_epilog.prim_id_param_offset); args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */ - args[5] = LLVMGetParam(ctx.radeon_bld.main_fn, + args[5] = LLVMGetParam(ctx.main_fn, VS_EPILOG_PRIMID_LOC); /* X */ args[6] = uint->undef; /* Y */ args[7] = uint->undef; /* Z */ @@ -7041,8 +6967,7 @@ static bool si_compile_vs_epilog(struct si_screen *sscreen, /* Compile. */ LLVMBuildRetVoid(gallivm->builder); - radeon_llvm_finalize_module( - &ctx.radeon_bld, + radeon_llvm_finalize_module(&ctx, r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_VERTEX)); if (si_compile_llvm(sscreen, &out->binary, &out->config, tm, @@ -7050,7 +6975,7 @@ static bool si_compile_vs_epilog(struct si_screen *sscreen, "Vertex Shader Epilog")) status = false; - radeon_llvm_dispose(&ctx.radeon_bld); + radeon_llvm_dispose(&ctx); return status; } @@ -7154,8 +7079,8 @@ static bool si_compile_tcs_epilog(struct si_screen *sscreen, union si_shader_part_key *key = &out->key; struct si_shader shader = {}; struct si_shader_context ctx; - struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm; - struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base; + struct gallivm_state *gallivm = &ctx.gallivm; + struct lp_build_tgsi_context *bld_base = &ctx.soa.bld_base; LLVMTypeRef params[16]; LLVMValueRef func; int last_sgpr, num_params; @@ -7187,7 +7112,7 @@ static bool si_compile_tcs_epilog(struct si_screen *sscreen, /* Create the function. */ si_create_function(&ctx, NULL, 0, params, num_params, last_sgpr); declare_tess_lds(&ctx); - func = ctx.radeon_bld.main_fn; + func = ctx.main_fn; si_write_tess_factors(bld_base, LLVMGetParam(func, last_sgpr + 1), @@ -7196,8 +7121,7 @@ static bool si_compile_tcs_epilog(struct si_screen *sscreen, /* Compile. */ LLVMBuildRetVoid(gallivm->builder); - radeon_llvm_finalize_module( - &ctx.radeon_bld, + radeon_llvm_finalize_module(&ctx, r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_TESS_CTRL)); if (si_compile_llvm(sscreen, &out->binary, &out->config, tm, @@ -7205,7 +7129,7 @@ static bool si_compile_tcs_epilog(struct si_screen *sscreen, "Tessellation Control Shader Epilog")) status = false; - radeon_llvm_dispose(&ctx.radeon_bld); + radeon_llvm_dispose(&ctx); return status; } @@ -7247,7 +7171,7 @@ static bool si_compile_ps_prolog(struct si_screen *sscreen, union si_shader_part_key *key = &out->key; struct si_shader shader = {}; struct si_shader_context ctx; - struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm; + struct gallivm_state *gallivm = &ctx.gallivm; LLVMTypeRef *params; LLVMValueRef ret, func; int last_sgpr, num_params, num_returns, i, num_color_channels; @@ -7280,7 +7204,7 @@ static bool si_compile_ps_prolog(struct si_screen *sscreen, /* Create the function. */ si_create_function(&ctx, params, num_returns, params, num_params, last_sgpr); - func = ctx.radeon_bld.main_fn; + func = ctx.main_fn; /* Copy inputs to outputs. This should be no-op, as the registers match, * but it will prevent the compiler from overwriting them unintentionally. @@ -7482,8 +7406,7 @@ static bool si_compile_ps_prolog(struct si_screen *sscreen, /* Compile. */ si_llvm_build_ret(&ctx, ret); - radeon_llvm_finalize_module( - &ctx.radeon_bld, + radeon_llvm_finalize_module(&ctx, r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT)); if (si_compile_llvm(sscreen, &out->binary, &out->config, tm, @@ -7491,7 +7414,7 @@ static bool si_compile_ps_prolog(struct si_screen *sscreen, "Fragment Shader Prolog")) status = false; - radeon_llvm_dispose(&ctx.radeon_bld); + radeon_llvm_dispose(&ctx); return status; } @@ -7507,8 +7430,8 @@ static bool si_compile_ps_epilog(struct si_screen *sscreen, union si_shader_part_key *key = &out->key; struct si_shader shader = {}; struct si_shader_context ctx; - struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm; - struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base; + struct gallivm_state *gallivm = &ctx.gallivm; + struct lp_build_tgsi_context *bld_base = &ctx.soa.bld_base; LLVMTypeRef params[16+8*4+3]; LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL; int last_sgpr, num_params, i; @@ -7546,7 +7469,7 @@ static bool si_compile_ps_epilog(struct si_screen *sscreen, /* Create the function. */ si_create_function(&ctx, NULL, 0, params, num_params, last_sgpr); /* Disable elimination of unused inputs. */ - radeon_llvm_add_attribute(ctx.radeon_bld.main_fn, + radeon_llvm_add_attribute(ctx.main_fn, "InitialPSInputAddr", 0xffffff); /* Process colors. */ @@ -7579,7 +7502,7 @@ static bool si_compile_ps_epilog(struct si_screen *sscreen, int mrt = u_bit_scan(&colors_written); for (i = 0; i < 4; i++) - color[i] = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++); + color[i] = LLVMGetParam(ctx.main_fn, vgpr++); si_export_mrt_color(bld_base, color, mrt, num_params - 1, @@ -7588,11 +7511,11 @@ static bool si_compile_ps_epilog(struct si_screen *sscreen, /* Process depth, stencil, samplemask. */ if (key->ps_epilog.writes_z) - depth = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++); + depth = LLVMGetParam(ctx.main_fn, vgpr++); if (key->ps_epilog.writes_stencil) - stencil = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++); + stencil = LLVMGetParam(ctx.main_fn, vgpr++); if (key->ps_epilog.writes_samplemask) - samplemask = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++); + samplemask = LLVMGetParam(ctx.main_fn, vgpr++); if (depth || stencil || samplemask) si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp); @@ -7604,8 +7527,7 @@ static bool si_compile_ps_epilog(struct si_screen *sscreen, /* Compile. */ LLVMBuildRetVoid(gallivm->builder); - radeon_llvm_finalize_module( - &ctx.radeon_bld, + radeon_llvm_finalize_module(&ctx, r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT)); if (si_compile_llvm(sscreen, &out->binary, &out->config, tm, @@ -7613,7 +7535,7 @@ static bool si_compile_ps_epilog(struct si_screen *sscreen, "Fragment Shader Epilog")) status = false; - radeon_llvm_dispose(&ctx.radeon_bld); + radeon_llvm_dispose(&ctx); return status; } diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h b/src/gallium/drivers/radeonsi/si_shader_internal.h index b46cc1c379d..37001c0a012 100644 --- a/src/gallium/drivers/radeonsi/si_shader_internal.h +++ b/src/gallium/drivers/radeonsi/si_shader_internal.h @@ -45,26 +45,32 @@ struct radeon_shader_binary; struct radeon_llvm_flow; -struct radeon_llvm_context { +struct si_shader_context { struct lp_build_tgsi_soa_context soa; + struct gallivm_state gallivm; + struct si_shader *shader; + struct si_screen *screen; - /*=== Front end configuration ===*/ - - /* Instructions that are not described by any of the TGSI opcodes. */ + unsigned type; /* PIPE_SHADER_* specifies the type of shader. */ + bool is_gs_copy_shader; + /* Whether to generate the optimized shader variant compiled as a whole + * (without a prolog and epilog) + */ + bool is_monolithic; /** This function is responsible for initilizing the inputs array and will be * called once for each input declared in the TGSI shader. */ - void (*load_input)(struct radeon_llvm_context *, + void (*load_input)(struct si_shader_context *, unsigned input_index, const struct tgsi_full_declaration *decl, LLVMValueRef out[4]); - void (*load_system_value)(struct radeon_llvm_context *, + void (*load_system_value)(struct si_shader_context *, unsigned index, const struct tgsi_full_declaration *decl); - void (*declare_memory_region)(struct radeon_llvm_context *, + void (*declare_memory_region)(struct si_shader_context *, const struct tgsi_full_declaration *decl); /** This array contains the input values for the shader. Typically these @@ -83,8 +89,6 @@ struct radeon_llvm_context { unsigned temps_count; LLVMValueRef system_values[RADEON_LLVM_MAX_SYSTEM_VALUES]; - /*=== Private Members ===*/ - struct radeon_llvm_flow *flow; unsigned flow_depth; unsigned flow_depth_max; @@ -97,16 +101,63 @@ struct radeon_llvm_context { LLVMValueRef main_fn; LLVMTypeRef return_type; + int param_streamout_config; + int param_streamout_write_index; + int param_streamout_offset[4]; + int param_vertex_id; + int param_rel_auto_id; + int param_vs_prim_id; + int param_instance_id; + int param_vertex_index0; + int param_tes_u; + int param_tes_v; + int param_tes_rel_patch_id; + int param_tes_patch_id; + int param_es2gs_offset; + int param_oc_lds; + + /* Sets a bit if the dynamic HS control word was 0x80000000. The bit is + * 0x800000 for VS, 0x1 for ES. + */ + int param_tess_offchip; + + LLVMTargetMachineRef tm; + + unsigned invariant_load_md_kind; + unsigned range_md_kind; + unsigned uniform_md_kind; unsigned fpmath_md_kind; LLVMValueRef fpmath_md_2p5_ulp; - - struct gallivm_state gallivm; + LLVMValueRef empty_md; + + /* Preloaded descriptors. */ + LLVMValueRef esgs_ring; + LLVMValueRef gsvs_ring[4]; + + LLVMValueRef lds; + LLVMValueRef gs_next_vertex[4]; + LLVMValueRef return_value; + + LLVMTypeRef voidt; + LLVMTypeRef i1; + LLVMTypeRef i8; + LLVMTypeRef i32; + LLVMTypeRef i64; + LLVMTypeRef i128; + LLVMTypeRef f32; + LLVMTypeRef v16i8; + LLVMTypeRef v2i32; + LLVMTypeRef v4i32; + LLVMTypeRef v4f32; + LLVMTypeRef v8i32; + + LLVMValueRef shared_memory; }; -static inline struct radeon_llvm_context * -radeon_llvm_context(struct lp_build_tgsi_context *bld_base) +static inline struct si_shader_context * +si_shader_context(struct lp_build_tgsi_context *bld_base) { - return (struct radeon_llvm_context*)bld_base; + return (struct si_shader_context*)bld_base; } void radeon_llvm_add_attribute(LLVMValueRef F, const char *name, int value); @@ -124,22 +175,22 @@ LLVMTypeRef tgsi2llvmtype(struct lp_build_tgsi_context *bld_base, LLVMValueRef bitcast(struct lp_build_tgsi_context *bld_base, enum tgsi_opcode_type type, LLVMValueRef value); -LLVMValueRef radeon_llvm_bound_index(struct radeon_llvm_context *ctx, +LLVMValueRef radeon_llvm_bound_index(struct si_shader_context *ctx, LLVMValueRef index, unsigned num); -void radeon_llvm_context_init(struct radeon_llvm_context *ctx, +void radeon_llvm_context_init(struct si_shader_context *ctx, const char *triple, const struct tgsi_shader_info *info, const struct tgsi_token *tokens); -void radeon_llvm_create_func(struct radeon_llvm_context *ctx, +void radeon_llvm_create_func(struct si_shader_context *ctx, LLVMTypeRef *return_types, unsigned num_return_elems, LLVMTypeRef *ParamTypes, unsigned ParamCount); -void radeon_llvm_dispose(struct radeon_llvm_context *ctx); +void radeon_llvm_dispose(struct si_shader_context *ctx); -void radeon_llvm_finalize_module(struct radeon_llvm_context *ctx, +void radeon_llvm_finalize_module(struct si_shader_context *ctx, bool run_verifier); LLVMValueRef radeon_llvm_emit_fetch_64bit(struct lp_build_tgsi_context *bld_base, diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c index 75ceb577b9c..1ee9afb4658 100644 --- a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c +++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c @@ -695,7 +695,7 @@ static void emit_fdiv(const struct lp_build_tgsi_action *action, struct lp_build_tgsi_context *bld_base, struct lp_build_emit_data *emit_data) { - struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); emit_data->output[emit_data->chan] = LLVMBuildFDiv(bld_base->base.gallivm->builder, diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c index e1534c717a0..b0174b116c2 100644 --- a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c +++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c @@ -285,7 +285,7 @@ LLVMValueRef bitcast(struct lp_build_tgsi_context *bld_base, * Return a value that is equal to the given i32 \p index if it lies in [0,num) * or an undefined value in the same interval otherwise. */ -LLVMValueRef radeon_llvm_bound_index(struct radeon_llvm_context *ctx, +LLVMValueRef radeon_llvm_bound_index(struct si_shader_context *ctx, LLVMValueRef index, unsigned num) { @@ -311,7 +311,7 @@ LLVMValueRef radeon_llvm_bound_index(struct radeon_llvm_context *ctx, } static struct radeon_llvm_flow * -get_current_flow(struct radeon_llvm_context *ctx) +get_current_flow(struct si_shader_context *ctx) { if (ctx->flow_depth > 0) return &ctx->flow[ctx->flow_depth - 1]; @@ -319,7 +319,7 @@ get_current_flow(struct radeon_llvm_context *ctx) } static struct radeon_llvm_flow * -get_innermost_loop(struct radeon_llvm_context *ctx) +get_innermost_loop(struct si_shader_context *ctx) { for (unsigned i = ctx->flow_depth; i > 0; --i) { if (ctx->flow[i - 1].loop_entry_block) @@ -329,7 +329,7 @@ get_innermost_loop(struct radeon_llvm_context *ctx) } static struct radeon_llvm_flow * -push_flow(struct radeon_llvm_context *ctx) +push_flow(struct si_shader_context *ctx) { struct radeon_llvm_flow *flow; @@ -380,7 +380,7 @@ get_temp_array_id(struct lp_build_tgsi_context *bld_base, unsigned reg_index, const struct tgsi_ind_register *reg) { - struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); unsigned num_arrays = ctx->soa.bld_base.info->array_max[TGSI_FILE_TEMPORARY]; unsigned i; @@ -402,7 +402,7 @@ get_array_range(struct lp_build_tgsi_context *bld_base, unsigned File, unsigned reg_index, const struct tgsi_ind_register *reg) { - struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct tgsi_declaration_range range; if (File == TGSI_FILE_TEMPORARY) { @@ -438,7 +438,7 @@ emit_array_index(struct lp_build_tgsi_soa_context *bld, * must be used. */ static LLVMValueRef -get_pointer_into_array(struct radeon_llvm_context *ctx, +get_pointer_into_array(struct si_shader_context *ctx, unsigned file, unsigned swizzle, unsigned reg_index, @@ -556,7 +556,7 @@ load_value_from_array(struct lp_build_tgsi_context *bld_base, unsigned reg_index, const struct tgsi_ind_register *reg_indirect) { - struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; LLVMBuilderRef builder = gallivm->builder; @@ -592,7 +592,7 @@ store_value_to_array(struct lp_build_tgsi_context *bld_base, unsigned reg_index, const struct tgsi_ind_register *reg_indirect) { - struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; LLVMBuilderRef builder = gallivm->builder; @@ -639,7 +639,7 @@ LLVMValueRef radeon_llvm_emit_fetch(struct lp_build_tgsi_context *bld_base, enum tgsi_opcode_type type, unsigned swizzle) { - struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base); LLVMBuilderRef builder = bld_base->base.gallivm->builder; LLVMValueRef result = NULL, ptr, ptr2; @@ -737,7 +737,7 @@ static LLVMValueRef fetch_system_value(struct lp_build_tgsi_context *bld_base, enum tgsi_opcode_type type, unsigned swizzle) { - struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; LLVMValueRef cval = ctx->system_values[reg->Register.Index]; @@ -751,7 +751,7 @@ static LLVMValueRef fetch_system_value(struct lp_build_tgsi_context *bld_base, static void emit_declaration(struct lp_build_tgsi_context *bld_base, const struct tgsi_full_declaration *decl) { - struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); LLVMBuilderRef builder = bld_base->base.gallivm->builder; unsigned first, last, i; switch(decl->Declaration.File) { @@ -944,7 +944,7 @@ void radeon_llvm_emit_store(struct lp_build_tgsi_context *bld_base, const struct tgsi_opcode_info *info, LLVMValueRef dst[4]) { - struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base); struct gallivm_state *gallivm = bld->bld_base.base.gallivm; const struct tgsi_full_dst_register *reg = &inst->Dst[0]; @@ -1045,7 +1045,7 @@ static void set_basicblock_name(LLVMBasicBlockRef bb, const char *base, int pc) /* Append a basic block at the level of the parent flow. */ -static LLVMBasicBlockRef append_basic_block(struct radeon_llvm_context *ctx, +static LLVMBasicBlockRef append_basic_block(struct si_shader_context *ctx, const char *name) { struct gallivm_state *gallivm = &ctx->gallivm; @@ -1076,7 +1076,7 @@ static void bgnloop_emit(const struct lp_build_tgsi_action *action, struct lp_build_tgsi_context *bld_base, struct lp_build_emit_data *emit_data) { - struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; struct radeon_llvm_flow *flow = push_flow(ctx); flow->loop_entry_block = append_basic_block(ctx, "LOOP"); @@ -1090,7 +1090,7 @@ static void brk_emit(const struct lp_build_tgsi_action *action, struct lp_build_tgsi_context *bld_base, struct lp_build_emit_data *emit_data) { - struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; struct radeon_llvm_flow *flow = get_innermost_loop(ctx); @@ -1101,7 +1101,7 @@ static void cont_emit(const struct lp_build_tgsi_action *action, struct lp_build_tgsi_context *bld_base, struct lp_build_emit_data *emit_data) { - struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; struct radeon_llvm_flow *flow = get_innermost_loop(ctx); @@ -1112,7 +1112,7 @@ static void else_emit(const struct lp_build_tgsi_action *action, struct lp_build_tgsi_context *bld_base, struct lp_build_emit_data *emit_data) { - struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; struct radeon_llvm_flow *current_branch = get_current_flow(ctx); LLVMBasicBlockRef endif_block; @@ -1132,7 +1132,7 @@ static void endif_emit(const struct lp_build_tgsi_action *action, struct lp_build_tgsi_context *bld_base, struct lp_build_emit_data *emit_data) { - struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; struct radeon_llvm_flow *current_branch = get_current_flow(ctx); @@ -1149,7 +1149,7 @@ static void endloop_emit(const struct lp_build_tgsi_action *action, struct lp_build_tgsi_context *bld_base, struct lp_build_emit_data *emit_data) { - struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; struct radeon_llvm_flow *current_loop = get_current_flow(ctx); @@ -1167,7 +1167,7 @@ static void if_cond_emit(const struct lp_build_tgsi_action *action, struct lp_build_emit_data *emit_data, LLVMValueRef cond) { - struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; struct radeon_llvm_flow *flow = push_flow(ctx); LLVMBasicBlockRef if_block; @@ -1211,7 +1211,7 @@ static void emit_immediate(struct lp_build_tgsi_context *bld_base, const struct tgsi_full_immediate *imm) { unsigned i; - struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); for (i = 0; i < 4; ++i) { ctx->soa.immediates[ctx->soa.num_immediates][i] = @@ -1221,7 +1221,7 @@ static void emit_immediate(struct lp_build_tgsi_context *bld_base, ctx->soa.num_immediates++; } -void radeon_llvm_context_init(struct radeon_llvm_context *ctx, const char *triple, +void radeon_llvm_context_init(struct si_shader_context *ctx, const char *triple, const struct tgsi_shader_info *info, const struct tgsi_token *tokens) { @@ -1302,7 +1302,7 @@ void radeon_llvm_context_init(struct radeon_llvm_context *ctx, const char *tripl bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit; } -void radeon_llvm_create_func(struct radeon_llvm_context *ctx, +void radeon_llvm_create_func(struct si_shader_context *ctx, LLVMTypeRef *return_types, unsigned num_return_elems, LLVMTypeRef *ParamTypes, unsigned ParamCount) { @@ -1325,7 +1325,7 @@ void radeon_llvm_create_func(struct radeon_llvm_context *ctx, LLVMPositionBuilderAtEnd(ctx->gallivm.builder, main_fn_body); } -void radeon_llvm_finalize_module(struct radeon_llvm_context *ctx, +void radeon_llvm_finalize_module(struct si_shader_context *ctx, bool run_verifier) { struct gallivm_state *gallivm = ctx->soa.bld_base.base.gallivm; @@ -1362,7 +1362,7 @@ void radeon_llvm_finalize_module(struct radeon_llvm_context *ctx, gallivm_dispose_target_library_info(target_library_info); } -void radeon_llvm_dispose(struct radeon_llvm_context *ctx) +void radeon_llvm_dispose(struct si_shader_context *ctx) { LLVMDisposeModule(ctx->soa.bld_base.base.gallivm->module); LLVMContextDispose(ctx->soa.bld_base.base.gallivm->context); -- 2.30.2