From 6e58fc56a5a396020cd299db11895120ec3da520 Mon Sep 17 00:00:00 2001 From: Iago Toral Quiroga Date: Fri, 3 Jul 2015 08:23:33 +0200 Subject: [PATCH] i965/nir: Dot not assign direct uniform locations first for vec4-based shaders In the vec4 backend we want uniform locations to be assigned consecutively since that way the offsets produced by nir_lower_io are exactly what we need to implement nir_intrinsic_load_uniform. Otherwise we would need a mapping to match the output of nir_lower_io to the actual uniform registers we need to use. Reviewed-by: Jason Ekstrand --- src/mesa/drivers/dri/i965/brw_nir.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_nir.c b/src/mesa/drivers/dri/i965/brw_nir.c index 8700cb71ad4..d81d82323bb 100644 --- a/src/mesa/drivers/dri/i965/brw_nir.c +++ b/src/mesa/drivers/dri/i965/brw_nir.c @@ -101,10 +101,16 @@ brw_create_nir(struct brw_context *brw, /* Get rid of split copies */ nir_optimize(nir); - nir_assign_var_locations_direct_first(nir, &nir->uniforms, - &nir->num_direct_uniforms, - &nir->num_uniforms, - is_scalar); + if (is_scalar) { + nir_assign_var_locations_direct_first(nir, &nir->uniforms, + &nir->num_direct_uniforms, + &nir->num_uniforms, + is_scalar); + } else { + nir_assign_var_locations(&nir->uniforms, + &nir->num_uniforms, + is_scalar); + } nir_assign_var_locations(&nir->inputs, &nir->num_inputs, is_scalar); nir_assign_var_locations(&nir->outputs, &nir->num_outputs, is_scalar); -- 2.30.2