From 6e6243e9834961993880e97c484c713d240e33bd Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 3 Dec 2014 16:32:55 +0100 Subject: [PATCH] transport: define FIS layouts --- lib/sata/link/cont.py | 12 ++--- lib/sata/std.py | 14 ++++- lib/sata/transport/.keep_me | 0 lib/sata/transport/__init__.py | 15 ++++++ lib/sata/transport/std.py | 96 ++++++++++++++++++++++++++++++++++ 5 files changed, 130 insertions(+), 7 deletions(-) delete mode 100644 lib/sata/transport/.keep_me create mode 100644 lib/sata/transport/__init__.py create mode 100644 lib/sata/transport/std.py diff --git a/lib/sata/link/cont.py b/lib/sata/link/cont.py index 6847f6db..447e9179 100644 --- a/lib/sata/link/cont.py +++ b/lib/sata/link/cont.py @@ -47,18 +47,18 @@ class SATACONTInserter(Module): ) ) - # scranbler (between CONT and next primitive) + # scrambler (between CONT and next primitive) scrambler = Scrambler() self.submodules += scrambler self.comb += [ - scrambler.reset.eq(ResetSignal()), #XXX: should be on COMINIT / COMRESET - scrambler.ce.eq(scrambler_insert & self.source.stb & self.source.ack) + scrambler.reset.eq(ResetSignal()), #XXX: should be reseted on COMINIT / COMRESET + scrambler.ce.eq(scrambler_insert & source.stb & source.ack) ] # Datapath self.comb += [ Record.connect(sink, source), - If(self.sink.stb, + If(sink.stb, If(cont_insert, source.charisk.eq(0b0001), source.data.eq(primitives["CONT"]) @@ -109,7 +109,7 @@ class SATACONTRemover(Module): self.comb += [ Record.connect(sink, source), If(cont_ongoing, - self.source.charisk.eq(0b0001), - self.source.data.eq(last_primitive) + source.charisk.eq(0b0001), + source.data.eq(last_primitive) ) ] diff --git a/lib/sata/std.py b/lib/sata/std.py index 32d7d03a..aac6a341 100644 --- a/lib/sata/std.py +++ b/lib/sata/std.py @@ -1,6 +1,6 @@ from migen.fhdl.std import * from migen.genlib.record import * -from migen.flow.actor import EndpointDescription, Sink, Source +from migen.flow.actor import * primitives = { "ALIGN" : 0x7B4A4ABC, @@ -47,3 +47,15 @@ def link_layout(dw): ("error", 1) ] return EndpointDescription(layout, packetized=True) + +def transport_tx_layout(dw): + layout = [ + ("d", dw) + ] + return EndpointDescription(layout, packetized=True) + +def transport_rx_layout(dw): + layout = [ + ("d", dw) + ] + return EndpointDescription(layout, packetized=True) diff --git a/lib/sata/transport/.keep_me b/lib/sata/transport/.keep_me deleted file mode 100644 index e69de29b..00000000 diff --git a/lib/sata/transport/__init__.py b/lib/sata/transport/__init__.py new file mode 100644 index 00000000..a9e0042e --- /dev/null +++ b/lib/sata/transport/__init__.py @@ -0,0 +1,15 @@ +from lib.sata.std import * +from lib.sata.transport.std import * + +class SATATransportLayerTX(Module): + def __init__(self): + self.sink = Sink(transport_layout(32)) + +class SATATransportLayerRX(Module): + def __init__(self): + self.sink = Sink(transport_layout(32)) + +class SATATransportLayer(Module): + def __init__(self): + self.submodules.tx = SATATransportLayerTX() + self.submodules.rx = SATATransportLayerRX() diff --git a/lib/sata/transport/std.py b/lib/sata/transport/std.py new file mode 100644 index 00000000..03b56b2d --- /dev/null +++ b/lib/sata/transport/std.py @@ -0,0 +1,96 @@ +fis_types = { + "REG_H2D": 0x27, + "REG_D2H": 0x34, + "DMA_ACTIVATE_D2H": 0x39, + "DMA_SETUP": 0x41, + "DATA": 0x46, + "PIO_SETUP_D2H": 0x5F +} + +class FISField(): + def __init__(self, dword, offset, width): + self.dword = dword + self.offset = offset + self.width = width + +fis_reg_h2d_len = 5 +fis_reg_h2d_layout = { + "type": FISField(0, 0, 8), + "pm_port": FISField(0, 8, 4), + "c": FISField(0, 15, 1), + "command": FISField(0, 16, 8), + "features_lsb": FISField(0, 24, 8), + + "lba_lsb": FISField(1, 0, 24), + "device": FISField(1, 24, 0), + + "lba_msb": FISField(2, 0, 24), + "features_msb": FISField(2, 24, 8), + + "count": FISField(3, 0, 16), + "icc": FISField(3, 16, 8), + "control": FISField(3, 24, 8) +} + +fis_reg_d2h_len = 5 +fis_reg_d2h_layout = { + "type": FISField(0, 0, 8), + "pm_port": FISField(0, 8, 4), + "i": FISField(0, 14, 1), + "status": FISField(0, 16, 8), + "error": FISField(0, 24, 8), + + "lba_lsb": FISField(1, 0, 24), + "device": FISField(1, 24, 0), + + "lba_msb": FISField(2, 0, 24), + + "count": FISField(3, 0, 16) +} + +fis_dma_activate_d2h_len = 1 +fis_dma_activate_d2h_layout = { + "type": FISField(0, 0, 8), + "pm_port": FISField(0, 8, 4) +} + +fis_dma_setup_len = 7 +fis_dma_setup_layout = { + "type": FISField(0, 0, 8), + "pm_port": FISField(0, 8, 4), + "d": FISField(0, 13, 1), + "i": FISField(0, 14, 1), + "a": FISField(0, 15, 1), + + "dma_buffer_id_low": FISField(1, 0, 32), + + "dma_buffer_id_high": FISField(2, 0, 32), + + "dma_buffer_offset": FISField(4, 0, 32), + + "dma_transfer_count": FISField(4, 0, 32) +} + +fis_data_layout = { + "type": FISField(0, 0, 8) +} + +fis_pio_setup_d2h_len = 5 +fis_pio_setup_d2h_layout = { + "type": FISField(0, 0, 8), + "pm_port": FISField(0, 8, 4), + "d": FISField(0, 13, 1), + "i": FISField(0, 14, 1), + "status": FISField(0, 16, 8), + "error": FISField(0, 24, 8), + + "lba_lsb": FISField(1, 0, 24), + "device": FISField(1, 24, 0), + + "lba_msb": FISField(2, 0, 24), + + "count": FISField(3, 0, 16), + "e_status": FISField(3, 24, 8), + + "transfer_count": FISField(4, 0, 16) +} -- 2.30.2