From 6e876c63ad580cb9643b529cf201b741a58219e3 Mon Sep 17 00:00:00 2001
From: Yann Sionneau <ys@m-labs.hk>
Date: Sun, 14 Jun 2015 23:19:27 +0200
Subject: [PATCH] pipistrello: fix FPGA speed grade

---
 mibuild/platforms/pipistrello.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/mibuild/platforms/pipistrello.py b/mibuild/platforms/pipistrello.py
index 127f609c..08c14827 100644
--- a/mibuild/platforms/pipistrello.py
+++ b/mibuild/platforms/pipistrello.py
@@ -130,7 +130,7 @@ class Platform(XilinxPlatform):
     default_clk_period = 20
 
     def __init__(self):
-        XilinxPlatform.__init__(self, "xc6slx45-csg324-2", _io, _connectors)
+        XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
         self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6"
 
     def create_programmer(self):
-- 
2.30.2