From 6e8c8b23001dd0f042e591e707a4a1cd3ddb5914 Mon Sep 17 00:00:00 2001 From: Dodji Seketeli Date: Tue, 31 May 2011 14:17:06 +0200 Subject: [PATCH] Revert "Fix PR debug/49047" This reverts commit ce20032a8ad4d9d4fa37192e2ecc73cb257094e8. From-SVN: r174473 --- gcc/ChangeLog | 6 -- gcc/dwarf2out.c | 6 -- gcc/testsuite/ChangeLog | 5 -- gcc/testsuite/g++.dg/debug/dwarf2/cdtor-1.C | 17 ----- libjava/ChangeLog | 11 --- libjava/configure.host | 4 +- libjava/sysdep/i386/locks.h | 54 ++++++++------ libjava/sysdep/x86-64/locks.h | 83 +++++++++++++++++++++ 8 files changed, 118 insertions(+), 68 deletions(-) delete mode 100644 gcc/testsuite/g++.dg/debug/dwarf2/cdtor-1.C create mode 100644 libjava/sysdep/x86-64/locks.h diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9ec727bf236..192845576e8 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,9 +1,3 @@ -2011-05-31 Dodji Seketeli - - PR debug/49047 - * dwarf2out.c (gen_subprogram_die): Emit linkage name attribute - for concrete functions containing the code of cloned functions. - 2011-05-31 Richard Guenther * tree-ssa-forwprop.c (forward_propagate_into_comparison): Rename diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c index 9a415e9a171..7ec1e931eed 100644 --- a/gcc/dwarf2out.c +++ b/gcc/dwarf2out.c @@ -19636,12 +19636,6 @@ gen_subprogram_die (tree decl, dw_die_ref context_die) subr_die = new_die (DW_TAG_subprogram, context_die, decl); add_abstract_origin_attribute (subr_die, origin); - /* This is where the actual code for a cloned function is. - Let's emit linkage name attribute for it. This helps - debuggers to e.g, set breakpoints into - constructors/destructors when the user asks "break - K::K". */ - add_linkage_name (subr_die, decl); } else if (old_die) { diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index dfa323b06ab..3f7b52abf18 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,8 +1,3 @@ -2011-05-31 Dodji Seketeli - - PR debug/49047 - * g++.dg/debug/dwarf2/cdtor-1.C: New test. - 2011-05-31 Ira Rosen PR testsuite/49239 diff --git a/gcc/testsuite/g++.dg/debug/dwarf2/cdtor-1.C b/gcc/testsuite/g++.dg/debug/dwarf2/cdtor-1.C deleted file mode 100644 index 6d39e54ae08..00000000000 --- a/gcc/testsuite/g++.dg/debug/dwarf2/cdtor-1.C +++ /dev/null @@ -1,17 +0,0 @@ -// origin PR debug/49047 -// { dg-options "-g -dA" } -// { dg-do compile } - -struct K -{ - K () { } - ~K () { } -}; - -int -main() -{ - K k; -} - -// { dg-final {scan-assembler-times "\[^\n\r\]*DW_AT_MIPS_linkage_name:" 2 } } diff --git a/libjava/ChangeLog b/libjava/ChangeLog index 4ca6cf4c4e0..c0b2fa7c323 100644 --- a/libjava/ChangeLog +++ b/libjava/ChangeLog @@ -1,14 +1,3 @@ -2011-05-31 H.J. Lu - - PR libgcj/49193 - * configure.host (sysdeps_dir): Set to i386 for x86_64. - - * sysdep/i386/locks.h (compare_and_swap): Call - __sync_bool_compare_and_swap. - (release_set): Call write_barrier (). - - * sysdep/x86-64/locks.h: Removed. - 2011-04-24 Gerald Pfeifer * README: Refer to our generic bug reporting page. diff --git a/libjava/configure.host b/libjava/configure.host index 9d4f2b6a1db..5b8847803b3 100644 --- a/libjava/configure.host +++ b/libjava/configure.host @@ -132,7 +132,7 @@ case "${host}" in slow_pthread_self=yes ;; x86_64-*) - sysdeps_dir=i386 + sysdeps_dir=x86-64 # For 64-bit we always use SSE registers for arithmetic, # which doesn't have the extra precision problems of the fpu. # But be careful about 32-bit multilibs. @@ -279,7 +279,7 @@ EOF slow_pthread_self= ;; i[34567]86-*-solaris2.1[0-9]* ) - sysdeps_dir=i386 + sysdeps_dir=x86-64 DIVIDESPEC=-f%{m32:no-}%{!m32:%{!m64:no-}}%{m64:}use-divide-subroutine ;; mips-sgi-irix6* ) diff --git a/libjava/sysdep/i386/locks.h b/libjava/sysdep/i386/locks.h index 7b99f0bd781..9d130b0f515 100644 --- a/libjava/sysdep/i386/locks.h +++ b/libjava/sysdep/i386/locks.h @@ -1,6 +1,6 @@ /* locks.h - Thread synchronization primitives. X86/x86-64 implementation. - Copyright (C) 2002, 2011 Free Software Foundation + Copyright (C) 2002 Free Software Foundation This file is part of libgcj. @@ -23,25 +23,19 @@ compare_and_swap(volatile obj_addr_t *addr, obj_addr_t old, obj_addr_t new_val) { - return __sync_bool_compare_and_swap (addr, old, new_val); -} - -// Ensure that subsequent instructions do not execute on stale -// data that was loaded from memory before the barrier. -// On X86/x86-64, the hardware ensures that reads are properly ordered. -inline static void -read_barrier() -{ -} - -// Ensure that prior stores to memory are completed with respect to other -// processors. -inline static void -write_barrier() -{ - /* x86-64/X86 does not reorder writes. We just need to ensure that - gcc also doesn't. */ - __asm__ __volatile__(" " : : : "memory"); + char result; +#ifdef __x86_64__ + __asm__ __volatile__("lock; cmpxchgq %2, %0; setz %1" + : "=m"(*(addr)), "=q"(result) + : "r" (new_val), "a"(old), "m"(*addr) + : "memory"); +#else + __asm__ __volatile__("lock; cmpxchgl %2, %0; setz %1" + : "=m"(*addr), "=q"(result) + : "r" (new_val), "a"(old), "m"(*addr) + : "memory"); +#endif + return (bool) result; } // Set *addr to new_val with release semantics, i.e. making sure @@ -52,7 +46,7 @@ write_barrier() inline static void release_set(volatile obj_addr_t *addr, obj_addr_t new_val) { - write_barrier (); + __asm__ __volatile__(" " : : : "memory"); *(addr) = new_val; } @@ -66,4 +60,22 @@ compare_and_swap_release(volatile obj_addr_t *addr, { return compare_and_swap(addr, old, new_val); } + +// Ensure that subsequent instructions do not execute on stale +// data that was loaded from memory before the barrier. +// On X86/x86-64, the hardware ensures that reads are properly ordered. +inline static void +read_barrier() +{ +} + +// Ensure that prior stores to memory are completed with respect to other +// processors. +inline static void +write_barrier() +{ + /* x86-64/X86 does not reorder writes. We just need to ensure that + gcc also doesn't. */ + __asm__ __volatile__(" " : : : "memory"); +} #endif diff --git a/libjava/sysdep/x86-64/locks.h b/libjava/sysdep/x86-64/locks.h new file mode 100644 index 00000000000..fdc0a3efb82 --- /dev/null +++ b/libjava/sysdep/x86-64/locks.h @@ -0,0 +1,83 @@ +/* locks.h - Thread synchronization primitives. X86/x86-64 implementation. + + Copyright (C) 2002 Free Software Foundation + + Contributed by Bo Thorsen . + + This file is part of libgcj. + +This software is copyrighted work licensed under the terms of the +Libgcj License. Please consult the file "LIBGCJ_LICENSE" for +details. */ + +#ifndef __SYSDEP_LOCKS_H__ +#define __SYSDEP_LOCKS_H__ + +typedef size_t obj_addr_t; /* Integer type big enough for object */ + /* address. */ + +// Atomically replace *addr by new_val if it was initially equal to old. +// Return true if the comparison succeeded. +// Assumed to have acquire semantics, i.e. later memory operations +// cannot execute before the compare_and_swap finishes. +inline static bool +compare_and_swap(volatile obj_addr_t *addr, + obj_addr_t old, + obj_addr_t new_val) +{ + char result; +#ifdef __x86_64__ + __asm__ __volatile__("lock; cmpxchgq %2, %0; setz %1" + : "=m"(*(addr)), "=q"(result) + : "r" (new_val), "a"(old), "m"(*addr) + : "memory"); +#else + __asm__ __volatile__("lock; cmpxchgl %2, %0; setz %1" + : "=m"(*addr), "=q"(result) + : "r" (new_val), "a"(old), "m"(*addr) + : "memory"); +#endif + return (bool) result; +} + +// Set *addr to new_val with release semantics, i.e. making sure +// that prior loads and stores complete before this +// assignment. +// On X86/x86-64, the hardware shouldn't reorder reads and writes, +// so we just have to convince gcc not to do it either. +inline static void +release_set(volatile obj_addr_t *addr, obj_addr_t new_val) +{ + __asm__ __volatile__(" " : : : "memory"); + *(addr) = new_val; +} + +// Compare_and_swap with release semantics instead of acquire semantics. +// On many architecture, the operation makes both guarantees, so the +// implementation can be the same. +inline static bool +compare_and_swap_release(volatile obj_addr_t *addr, + obj_addr_t old, + obj_addr_t new_val) +{ + return compare_and_swap(addr, old, new_val); +} + +// Ensure that subsequent instructions do not execute on stale +// data that was loaded from memory before the barrier. +// On X86/x86-64, the hardware ensures that reads are properly ordered. +inline static void +read_barrier() +{ +} + +// Ensure that prior stores to memory are completed with respect to other +// processors. +inline static void +write_barrier() +{ + /* x86-64/X86 does not reorder writes. We just need to ensure that + gcc also doesn't. */ + __asm__ __volatile__(" " : : : "memory"); +} +#endif -- 2.30.2