From 6e8e36d17bf1e2d485aaab5e92945586fe4b4259 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Fri, 5 Mar 2021 11:14:02 +0100 Subject: [PATCH] Added support files for ls180+SRAM on TSMC 180nm. --- experiments9/tsmc_c018/SPBlock_512W64B8W.v | 7 ++ experiments9/tsmc_c018/SPBlock_512W64B8W.vbe | 19 +++++ experiments9/tsmc_c018/build_full_4ksram.sh | 29 +++++++ experiments9/tsmc_c018/coriolis2/__init__.py | 0 experiments9/tsmc_c018/coriolis2/ioring.py | 42 +++++++++++ experiments9/tsmc_c018/coriolis2/katana.py | 6 ++ experiments9/tsmc_c018/coriolis2/pinparse.py | 1 + experiments9/tsmc_c018/coriolis2/settings.py | 79 ++++++++++++++++++++ experiments9/tsmc_c018/doDesign.py | 77 +++++++++++++++++++ experiments9/tsmc_c018/non_generated | 1 + 10 files changed, 261 insertions(+) create mode 100644 experiments9/tsmc_c018/SPBlock_512W64B8W.v create mode 100644 experiments9/tsmc_c018/SPBlock_512W64B8W.vbe create mode 100755 experiments9/tsmc_c018/build_full_4ksram.sh create mode 100644 experiments9/tsmc_c018/coriolis2/__init__.py create mode 100644 experiments9/tsmc_c018/coriolis2/ioring.py create mode 100644 experiments9/tsmc_c018/coriolis2/katana.py create mode 120000 experiments9/tsmc_c018/coriolis2/pinparse.py create mode 100644 experiments9/tsmc_c018/coriolis2/settings.py create mode 100644 experiments9/tsmc_c018/doDesign.py create mode 120000 experiments9/tsmc_c018/non_generated diff --git a/experiments9/tsmc_c018/SPBlock_512W64B8W.v b/experiments9/tsmc_c018/SPBlock_512W64B8W.v new file mode 100644 index 0000000..ddab968 --- /dev/null +++ b/experiments9/tsmc_c018/SPBlock_512W64B8W.v @@ -0,0 +1,7 @@ +(* blackbox = 1 *) +module SPBlock_512W64B8W(input [8:0] a, + input [63:0] d, + output [63:0] q, + input [7:0] we, + input clk); +endmodule // SPBlock_512W64B8W diff --git a/experiments9/tsmc_c018/SPBlock_512W64B8W.vbe b/experiments9/tsmc_c018/SPBlock_512W64B8W.vbe new file mode 100644 index 0000000..c752468 --- /dev/null +++ b/experiments9/tsmc_c018/SPBlock_512W64B8W.vbe @@ -0,0 +1,19 @@ + +-- Phony VHDL interface for SRAM block. + +entity SPBlock_512W64B8W is + port ( clk : in bit + ; we : in bit_vector( 7 downto 0) + ; a : in bit_vector( 8 downto 0) + ; d : in bit_vector(63 downto 0) + ; q : out bit_vector(63 downto 0) + ; vdd : in bit + ; vss : in bit + ); +end SPBlock_512W64B8W; + +architecture behavioral of SPBlock_512W64B8W is + +begin + +end behavioral; diff --git a/experiments9/tsmc_c018/build_full_4ksram.sh b/experiments9/tsmc_c018/build_full_4ksram.sh new file mode 100755 index 0000000..c63e814 --- /dev/null +++ b/experiments9/tsmc_c018/build_full_4ksram.sh @@ -0,0 +1,29 @@ +#!/bin/sh + +# full core build including QTY 4of 4k SRAMs: please remember to alter +# doDesign.py before running! +# change the settings to the larger chip/corona size +echo "remember to check doDesign core size" + +# initialise/update the pinmux submodule +git submodule update --init --remote + +# makes symlinks to alliance +./mksyms.sh + +# generates the io pads needed for ioring.py +make pinmux + +# clear out +make clean +rm *.vst *.ap + +# copies over a "full" core +cp non_generated/full_core_4_4ksram_ls180.il ls180.il + +# make the vst from ilang +make vst + +# starts the build. +make lvx + diff --git a/experiments9/tsmc_c018/coriolis2/__init__.py b/experiments9/tsmc_c018/coriolis2/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/experiments9/tsmc_c018/coriolis2/ioring.py b/experiments9/tsmc_c018/coriolis2/ioring.py new file mode 100644 index 0000000..ddebb71 --- /dev/null +++ b/experiments9/tsmc_c018/coriolis2/ioring.py @@ -0,0 +1,42 @@ +#!/usr/bin/env python + +from helpers import l, u, n +import os +import json + +def _byteify(data, ignore_dicts = False): + # if this is a unicode string, return its string representation + if isinstance(data, unicode): + return data.encode('utf-8') + # if this is a list of values, return list of byteified values + if isinstance(data, list): + return [ _byteify(item, ignore_dicts=True) for item in data ] + # if this is a dictionary, return dictionary of byteified keys and values + # but only if we haven't already byteified it + if isinstance(data, dict) and not ignore_dicts: + return dict((_byteify(key, ignore_dicts=True), + _byteify(value, ignore_dicts=True)) + for key, value in data.iteritems()) + # if it's anything else, return it in its original form + return data + +# load JSON-formatted pad info from pinmux +pth = os.path.abspath(__file__) +pth = os.path.split(pth)[0] +print "path", pth +with open("%s/ls180/litex_pinpads.json" % pth) as f: + txt = f.read() +chip = json.loads(txt, object_hook=_byteify) +chip = _byteify(chip, ignore_dicts=True) +print chip + +chip.update({ 'pads.ioPadGauge' : 'pxlib', + # core option (big, time-consuming) + #'core.size' : ( l(28000), l(28000) ), + #'chip.size' : ( l(30200), l(30200) ), + # no-core option (test_issuer but no actual core) + 'core.size' : ( l(13000), l(13000) ), + 'chip.size' : ( l(14400), l(14400) ), + 'pads.useCoreSize': True, + 'chip.clockTree' : True, + }) diff --git a/experiments9/tsmc_c018/coriolis2/katana.py b/experiments9/tsmc_c018/coriolis2/katana.py new file mode 100644 index 0000000..7a5103f --- /dev/null +++ b/experiments9/tsmc_c018/coriolis2/katana.py @@ -0,0 +1,6 @@ +from Hurricane import DebugSession + +#DebugSession.addToTrace( katana.getCell().getNet( 'cu_issue_i' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'cu_wr_rel_o(2)' ) ) +#DebugSession.addToTrace( katana.getCell().getNet( 'xer_so_ok' ) ) + diff --git a/experiments9/tsmc_c018/coriolis2/pinparse.py b/experiments9/tsmc_c018/coriolis2/pinparse.py new file mode 120000 index 0000000..a704604 --- /dev/null +++ b/experiments9/tsmc_c018/coriolis2/pinparse.py @@ -0,0 +1 @@ +../pinmux/src/parse.py \ No newline at end of file diff --git a/experiments9/tsmc_c018/coriolis2/settings.py b/experiments9/tsmc_c018/coriolis2/settings.py new file mode 100644 index 0000000..5c1ea66 --- /dev/null +++ b/experiments9/tsmc_c018/coriolis2/settings.py @@ -0,0 +1,79 @@ +# -*- Mode:Python -*- + +import Cfg +import CRL +import Viewer +from helpers.overlay import CfgCache +import symbolic.cmos45 # do not remove +import os + +if os.environ.has_key('CELLS_TOP'): + cellsTop = os.environ['CELLS_TOP'] +else: + cellsTop = '../../../alliance-check-toolkit/cells' + +with CfgCache('', priority=Cfg.Parameter.Priority.UserFile) as cfg: + cfg.misc.catchCore = False + cfg.misc.info = False + cfg.misc.paranoid = False + cfg.misc.bug = False + cfg.misc.logMode = True + cfg.misc.verboseLevel1 = True + cfg.misc.verboseLevel2 = True + cfg.anabatic.edgeLenght = 24 + cfg.anabatic.edgeWidth = 8 + cfg.anabatic.topRoutingLayer = 'METAL5' + cfg.etesian.graphics = 3 + + #cfg.katana.searchHalo = 30 + #cfg.katana.eventsLimit = 1000000 + #cfg.katana.hTracksReservedLocal = 7 + + # Run 2 (make-cgt-2.log) + #cfg.etesian.effort = 2 + #cfg.etesian.uniformDensity = True + #cfg.etesian.spaceMargin = 0.05 + #cfg.etesian.aspectRatio = 1.0 + #cfg.katana.vTracksReservedLocal = 4 + #cfg.katana.hTracksReservedLocal = 4 + + # Run 3 (make-cgt-3.log) + #cfg.etesian.effort = 2 + #cfg.etesian.uniformDensity = False + #cfg.etesian.spaceMargin = 0.05 + #cfg.etesian.aspectRatio = 1.0 + #cfg.katana.vTracksReservedLocal = 5 + #cfg.katana.hTracksReservedLocal = 5 + + # Run 4 (make-cgt-4.log) + #cfg.etesian.effort = 2 + #cfg.etesian.uniformDensity = True + #cfg.etesian.spaceMargin = 0.05 + #cfg.etesian.aspectRatio = 1.0 + + # Run 5 (make-cgt-5.log) + cfg.etesian.effort = 2 + cfg.etesian.uniformDensity = True + cfg.etesian.spaceMargin = 0.05 + cfg.etesian.aspectRatio = 1.0 + cfg.katana.useGlobalEstimate = False + cfg.katana.vTracksReservedLocal = 7 + cfg.katana.hTracksReservedLocal = 6 + cfg.katana.bloatOverloadAdd = 4 + cfg.conductor.stopLevel = 0 + cfg.conductor.maxPlaceIterations = 2 + cfg.conductor.useFixedAbHeight = False + + env = CRL.AllianceFramework.get().getEnvironment() + env.setCLOCK( '^sys_clk$|^ck|^jtag_tck$' ) + env.addSYSTEM_LIBRARY(library=cellsTop+'/niolib', + mode=CRL.Environment.Prepend ) + env.addSYSTEM_LIBRARY(library=cellsTop+'/nsxlib', + mode=CRL.Environment.Prepend ) + env.setPOWER ('vdd') + env.setGROUND('vss') + +Viewer.Graphics.setStyle('Alliance.Classic [black]') + +print( ' o Successfully run "<>/coriolis2/settings.py".' ) +print( ' - CELLS_TOP = "{}"'.format(cellsTop) ) diff --git a/experiments9/tsmc_c018/doDesign.py b/experiments9/tsmc_c018/doDesign.py new file mode 100644 index 0000000..76651a7 --- /dev/null +++ b/experiments9/tsmc_c018/doDesign.py @@ -0,0 +1,77 @@ + +from __future__ import print_function + +import os +import json +import sys +import traceback +import CRL +import helpers +from helpers.io import ErrorMessage, WarningMessage +from helpers import trace, l, u, n +import plugins +from Hurricane import DbU +from plugins.alpha.block.configuration import IoPin, GaugeConf +from plugins.alpha.block.iospecs import IoSpecs +from plugins.alpha.block.block import Block +from plugins.alpha.core2chip.libresocio import CoreToChip +from plugins.alpha.chip.configuration import ChipConf +from plugins.alpha.chip.chip import Chip + + +af = CRL.AllianceFramework.get() + +def scriptMain (**kw): + """The mandatory function to be called by Coriolis CGT/Unicorn.""" + global af + rvalue = True + coreSize = 5200.0 + chipBorder = 2*214.0 + 10*13.0 + ioSpecs = IoSpecs() + ioSpecs.loadFromPinmux( './non_generated/litex_pinpads.json' ) + try: + #helpers.setTraceLevel( 550 ) + cell, editor = plugins.kwParseMain( **kw ) + cell = af.getCell( 'ls180', CRL.Catalog.State.Logical ) + if cell is None: + print( ErrorMessage( 2, 'doDesign.scriptMain(): Unable to load cell "{}".' \ + .format('ls180') )) + sys.exit(1) + if editor: editor.setCell( cell ) + ls180Conf = ChipConf( cell, ioPads=ioSpecs.ioPadsSpec ) + ls180Conf.cfg.etesian.bloat = 'nsxlib' + ls180Conf.cfg.etesian.uniformDensity = True + ls180Conf.cfg.etesian.aspectRatio = 1.0 + ls180Conf.cfg.etesian.spaceMargin = 0.05 + ls180Conf.cfg.anabatic.searchHalo = 2 + ls180Conf.cfg.anabatic.globalIterations = 20 + ls180Conf.cfg.anabatic.topRoutingLayer = 'METAL5' + ls180Conf.cfg.katana.hTracksReservedLocal = 6 + ls180Conf.cfg.katana.vTracksReservedLocal = 3 + ls180Conf.cfg.katana.hTracksReservedMin = 3 + ls180Conf.cfg.katana.vTracksReservedMin = 1 + ls180Conf.cfg.block.spareSide = u(200) + ls180Conf.cfg.chip.supplyRailWidth = u(35) + ls180Conf.cfg.chip.supplyRailPitch = u(90) + ls180Conf.editor = editor + ls180Conf.useSpares = True + ls180Conf.useClockTree = True + ls180Conf.useHFNS = False + ls180Conf.bColumns = 2 + ls180Conf.bRows = 2 + ls180Conf.chipConf.name = 'chip' + ls180Conf.chipConf.ioPadGauge = 'LibreSOCIO' + ls180Conf.coreSize = (u(coreSize), u(coreSize)) + ls180Conf.chipSize = (u(coreSize + chipBorder), u(coreSize + chipBorder)) + ls180ToChip = CoreToChip( ls180Conf ) + ls180ToChip.buildChip() + chipBuilder = Chip( ls180Conf ) + rvalue = chipBuilder.doPnR() + chipBuilder.save() + CRL.Gds.save( ls180Conf.chip ) + except Exception, e: + helpers.io.catch(e) + rvalue = False + sys.stdout.flush() + sys.stderr.flush() + return rvalue diff --git a/experiments9/tsmc_c018/non_generated b/experiments9/tsmc_c018/non_generated new file mode 120000 index 0000000..f4c261f --- /dev/null +++ b/experiments9/tsmc_c018/non_generated @@ -0,0 +1 @@ +../non_generated \ No newline at end of file -- 2.30.2