From 6e9bf1e205f03c1d2c2a0259b1e05c21cb186949 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 16 Nov 2021 00:51:03 +0000 Subject: [PATCH] aiyaaaargh, re-route data through pad/core ports, no idea what to do --- src/spec/testing_stage1.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/spec/testing_stage1.py b/src/spec/testing_stage1.py index dcf8bf6..81f444a 100644 --- a/src/spec/testing_stage1.py +++ b/src/spec/testing_stage1.py @@ -260,9 +260,10 @@ class ASICPlatform(TemplatedPlatform): print (" pad", padres, padpin, padport, attrs) print (" padpin", padpin.layout) print (" jtag", io.core.layout, io.pad.layout) - m.d.comb += padpin.i.eq(self._invert_if(invert, port)) + m.d.comb += pin.i.eq(self._invert_if(invert, port)) + m.d.comb += padpin.i.eq(padport) m.d.comb += padport.io.eq(io.core.i) - m.d.comb += pin.i.eq(io.pad.i) + m.d.comb += io.pad.i.eq(pin.i) return m def get_output(self, pin, port, attrs, invert): @@ -282,7 +283,8 @@ class ASICPlatform(TemplatedPlatform): print (" pin", padpin.layout) print (" jtag", io.core.layout, io.pad.layout) m.d.comb += port.eq(self._invert_if(invert, pin.o)) - m.d.comb += padport.io.eq(io.core.o) + m.d.comb += padport.io.eq(self._invert_if(invert, padpin.o)) + m.d.comb += io.core.o.eq(port.io) m.d.comb += padpin.o.eq(io.pad.o) return m -- 2.30.2