From 6ef31bd15eec7467ef7659c98578e5c387776ab9 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 23 May 2022 20:04:35 +0100 Subject: [PATCH] --- openpower/sv/cr_int_predication.mdwn | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn index 78157e1d1..9da87f9a5 100644 --- a/openpower/sv/cr_int_predication.mdwn +++ b/openpower/sv/cr_int_predication.mdwn @@ -60,10 +60,16 @@ Purpose: * To provide a vectorised version of the same, suitable for advanced predication -Side-effects: +Useful side-effects: -* mtcrweird when RA=0 is a means to set or clear arbitrary CR bits +* mtcrweird when RA=0 is a means to set or clear + multiple arbitrary CR Field bits simultaneously, using immediates embedded within the instruction. +* With SVP64 on the weird instructions there is bit-for-bit interaction + between GPR predicate masks (r3, r10, r31) and the source + or destination GPR, in ways that are not possible with other + SVP64 instructions because normal SVP64 is bit-per-element. + On these weird instructions the element in effect *is* a bit. # Bit ordering. -- 2.30.2