From 6f3e5297dbf1a0b28e6bfa51990f957939d722d7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 17 Apr 2019 15:04:46 -0700 Subject: [PATCH] Add "-device" argument to synth_ice40 --- techlibs/ice40/Makefile.inc | 6 ++++-- techlibs/ice40/{abc.box => hx8k.box} | 4 ++-- techlibs/ice40/{abc.lut => hx8k.lut} | 2 +- techlibs/ice40/synth_ice40.cc | 15 +++++++++++++-- 4 files changed, 20 insertions(+), 7 deletions(-) rename techlibs/ice40/{abc.box => hx8k.box} (70%) rename techlibs/ice40/{abc.lut => hx8k.lut} (64%) diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc index abfede011..efcea6e98 100644 --- a/techlibs/ice40/Makefile.inc +++ b/techlibs/ice40/Makefile.inc @@ -28,9 +28,11 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v)) -$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.box)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.v)) -$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc.lut)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx8k.box)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/hx8k.lut)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/up5k.box)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/up5k.lut)) $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh)) $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh)) diff --git a/techlibs/ice40/abc.box b/techlibs/ice40/hx8k.box similarity index 70% rename from techlibs/ice40/abc.box rename to techlibs/ice40/hx8k.box index d775efa78..c31f7bf39 100644 --- a/techlibs/ice40/abc.box +++ b/techlibs/ice40/hx8k.box @@ -1,4 +1,4 @@ -# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt +# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt # NB: Inputs/Outputs must be ordered alphabetically @@ -10,4 +10,4 @@ SB_CARRY 1 1 3 1 # Inputs: I0 I1 I2 I3 # Outputs: O SB_LUT4 2 1 4 1 -316 379 400 449 +449 400 379 316 diff --git a/techlibs/ice40/abc.lut b/techlibs/ice40/hx8k.lut similarity index 64% rename from techlibs/ice40/abc.lut rename to techlibs/ice40/hx8k.lut index eef997869..3b3bb11e2 100644 --- a/techlibs/ice40/abc.lut +++ b/techlibs/ice40/hx8k.lut @@ -1,4 +1,4 @@ -# From https://github.com/cliffordwolf/icestorm/blob/81c33a3/icefuzz/timings_hx8k.txt +# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt # I3 I2 I1 I0 1 1 316 2 1 316 379 diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 91cd063a2..2981875eb 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -37,6 +37,10 @@ struct SynthIce40Pass : public ScriptPass log("\n"); log("This command runs synthesis for iCE40 FPGAs.\n"); log("\n"); + log(" -device < hx1k | lp384 | lp1k | lp8k | hx8k | u4k | up5k >\n"); + log(" optimise the synthesis netlist for the specified device.\n"); + log(" HX1K is the default target if no device argument specified.\n"); + log("\n"); log(" -top \n"); log(" use the specified module as top module\n"); log("\n"); @@ -102,7 +106,7 @@ struct SynthIce40Pass : public ScriptPass } - string top_opt, blif_file, edif_file, json_file, abc; + string top_opt, blif_file, edif_file, json_file, abc, device_opt; bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr; int min_ce_use; @@ -124,6 +128,7 @@ struct SynthIce40Pass : public ScriptPass abc2 = false; vpr = false; abc = "abc"; + device_opt = "hx1k"; } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -210,12 +215,18 @@ struct SynthIce40Pass : public ScriptPass abc = "abc9"; continue; } + if (args[argidx] == "-device" && argidx+1 < args.size()) { + device_opt = args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); + if (device_opt != "hx1k" && device_opt !="lp384" && device_opt != "lp1k" && device_opt !="lp8k" && device_opt !="hx8k" && device_opt != "u4k" && device_opt != "up5k") + log_cmd_error("Invalid or no family specified: '%s'\n", device_opt.c_str()); log_header(design, "Executing SYNTH_ICE40 pass.\n"); log_push(); @@ -319,7 +330,7 @@ struct SynthIce40Pass : public ScriptPass if (abc == "abc9") { run("read_verilog +/ice40/abc.v"); run("techmap -map +/techmap.v A:abc_box_id"); - run(abc + " -dress -lut +/ice40/abc.lut -box +/ice40/abc.box", "(skip if -noabc)"); + run(abc + stringf(" -dress -lut +/ice40/%s.lut -box +/ice40/%s.box", device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)"); run("blackbox A:abc_box_id"); } else -- 2.30.2