From 6f3f622fd9f95a8fe3bb623db0b4b3dfefc8cbce Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 26 Dec 2020 03:12:09 +0000 Subject: [PATCH] --- openpower/sv/overview.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index e706adf49..a0901875d 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -527,7 +527,7 @@ This is a minor variant on the CR-based predicate-result mode. Where pred-resul if not RC1: iregs[RT+i] = result if RC1 or Rc=1: crregs[offs+i] = CRnew -This is particularly useful, again, for FP operations that might overflow, where it is desirable to end the loop early, but also desirable to complete at least those operations that were okay (passed the test) without also having to sllow down execution by adding extra instructions that tested for the possibility of that failure, in advance of doing the actual calculation. +This is particularly useful, again, for FP operations that might overflow, where it is desirable to end the loop early, but also desirable to complete at least those operations that were okay (passed the test) without also having to slow down execution by adding extra instructions that tested for the possibility of that failure, in advance of doing the actual calculation. The only minor downside here though is the change to VL, which in some implementations may cause pipeline stalls. This was one of the reasons why CR-based pred-result analysis was added, because that at least is entirely paralleliseable. -- 2.30.2