From 6f4ac7b418c64f03f05e496953fe0c1d09864ab9 Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Sat, 24 Jun 2017 00:51:13 -0400 Subject: [PATCH] nvc0: enable bindless on kepler All the functionality is in. Maxwell will take a little bit more enablement work. Signed-off-by: Ilia Mirkin --- docs/features.txt | 2 +- docs/relnotes/17.4.0.html | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 6 +++--- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/docs/features.txt b/docs/features.txt index eed30763726..a5f34edd419 100644 --- a/docs/features.txt +++ b/docs/features.txt @@ -293,7 +293,7 @@ GLES3.2, GLSL ES 3.2 -- all DONE: i965/gen9+ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES version: - GL_ARB_bindless_texture DONE (radeonsi) + GL_ARB_bindless_texture DONE (nvc0, radeonsi) GL_ARB_cl_event not started GL_ARB_compute_variable_group_size DONE (nvc0, radeonsi) GL_ARB_ES3_2_compatibility DONE (i965/gen8+) diff --git a/docs/relnotes/17.4.0.html b/docs/relnotes/17.4.0.html index b477c274fe1..1adbb3e1cfe 100644 --- a/docs/relnotes/17.4.0.html +++ b/docs/relnotes/17.4.0.html @@ -50,6 +50,7 @@ Note: some of the new features are only available with certain drivers.
  • GL_ARB_shader_storage_buffer_object on r600/evergreen+
  • GL_ARB_compute_shader on r600/evergreen+
  • GL_ARB_cull_distance on r600/evergreen+
  • +
  • GL_ARB_bindless_texture on nvc0/kepler
  • OpenGL 4.3 on r600/evergreen with hw fp64 support
  • Support 1 binary format for GL_ARB_get_program_binary on i965
  • diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index e51d5163539..d911884f78e 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c @@ -258,8 +258,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX: case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: return 1; - case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: - return (class_3d >= NVE4_3D_CLASS) ? 1 : 0; case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0; case PIPE_CAP_TGSI_FS_FBFETCH: @@ -269,8 +267,11 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: case PIPE_CAP_POST_DEPTH_COVERAGE: return class_3d >= GM200_3D_CLASS; + case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: case PIPE_CAP_TGSI_BALLOT: return class_3d >= NVE4_3D_CLASS; + case PIPE_CAP_BINDLESS_TEXTURE: + return class_3d >= NVE4_3D_CLASS && class_3d < GM107_3D_CLASS; /* unsupported caps */ case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: @@ -300,7 +301,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY: case PIPE_CAP_INT64_DIVMOD: case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: - case PIPE_CAP_BINDLESS_TEXTURE: case PIPE_CAP_NIR_SAMPLERS_AS_DEREF: case PIPE_CAP_QUERY_SO_OVERFLOW: case PIPE_CAP_MEMOBJ: -- 2.30.2