From 6f548727fed3e049007e71c7fcf8a9029c9a387b Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 18 May 2022 13:01:12 +0100 Subject: [PATCH] --- openpower/sv/cr_int_predication.mdwn | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn index 957f9aa93..e60f6a921 100644 --- a/openpower/sv/cr_int_predication.mdwn +++ b/openpower/sv/cr_int_predication.mdwn @@ -113,9 +113,11 @@ bit 19=0, bit 20=0 n3 = mask[3] & (mode[3] == creg[3]) result = n0|n1|n2|n3 if M else n0&n1&n2&n3 RT[63] = result # MSB0 numbering, 63 is LSB - + If Rc: + CR0 = analyse(RT) + When used with SVP64 Prefixing this is a [[openpower/sv/normal]] -SVP64 type operation and as such can use RC1 Data-dependent +SVP64 type operation and as such can use Rc=1 and RC1 Data-dependent Mode capability **mfcrrweird** @@ -133,10 +135,16 @@ bit 19=0, bit 20=0 n3 = mask[3] & (mode[3] == creg[3]) result = n0||n1||n2||n3 RT[60:63] = result # MSB0 numbering, 63 is LSB + If Rc: + CR0 = analyse(RT) When used with SVP64 Prefixing this is a [[openpower/sv/normal]] -SVP64 type operation and as such can use RC1 Data-dependent -Mode capability +SVP64 type operation and as such can use Rc=1 and RC1 Data-dependent +Mode capability. + +Also as noted below, element-width override bits normally used +on the source is instead used to allow multiple results to be packed +into the destination. *Destination elwidth overrides still apply* **mtcrrweird** -- 2.30.2