From 6f5bf0292e2886f00ccf6c09a64a1b198ed33383 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 5 Nov 2015 15:06:33 +0800 Subject: [PATCH] fhdl/verilog: create clock domains in deterministic order --- migen/fhdl/verilog.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 72888999..19bba1fa 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -323,7 +323,7 @@ def convert(f, ios=None, name="top", if ios is None: ios = set() - for cd_name in list_clock_domains(f): + for cd_name in sorted(list_clock_domains(f)): try: f.clock_domains[cd_name] except KeyError: -- 2.30.2