From 6f7a74eaccc787ca0f742c076d47beb6834489e7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 8 Dec 2021 12:30:56 +0000 Subject: [PATCH] absolute import again --- src/openpower/decoder/test/pysim.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/openpower/decoder/test/pysim.py b/src/openpower/decoder/test/pysim.py index 0d70032b..531a7e83 100644 --- a/src/openpower/decoder/test/pysim.py +++ b/src/openpower/decoder/test/pysim.py @@ -6,7 +6,7 @@ from vcd.gtkw import GTKWSave from nmigen.hdl import ClockSignal, ResetSignal from nmigen.hdl.ast import SignalDict from nmigen.sim._base import BaseSignalState, BaseSimulation, BaseEngine -from _pyrtl import _FragmentCompiler +from openpower.decoder.test._pyrtl import _FragmentCompiler from nmigen.sim._pycoro import PyCoroProcess from nmigen.sim._pyclock import PyClockProcess -- 2.30.2