From 6f9d46e39ca86e08fefc9b64a14412acad79215e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 22 Jul 2022 14:04:21 +0100 Subject: [PATCH] add fault-first link to ARM SVE2 --- openpower/sv/comparison_table.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn index 6f4e1e179..16f0edfd6 100644 --- a/openpower/sv/comparison_table.mdwn +++ b/openpower/sv/comparison_table.mdwn @@ -11,7 +11,7 @@ * {3}: SVP64 provides the Vector register concept on top of the *Scalar* GPR, FPR and CR register files * {4}: SVP64 Vectorises Scalar instructions. When applied to e.g. VSX QP instructions, SVP64 "gains" 128-bit. * {5}: big-integer add is just `sv.adde`. Mul and divide require addition of two scalar operations -* {6} See [[sv/svp64/appendix]] +* {6} See [[sv/svp64/appendix]] and [ARM SVE Fault-First](https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf) * {7} Based on LD/ST Fail-first, extended to data. See [[sv/svp64/appendix]] * {8} Turns standard ops into a type of "cmp". See [[sv/svp64/appendix]] * {9} VSX's Vector Registers are mis-named: they are PackedSIMD. -- 2.30.2