From 6fea780f698a10ec43d4f69b49fe36c176ecd69b Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 3 Jun 2020 12:29:02 +0100
Subject: [PATCH] move over to using power_regspec_map.py from PowerDecode2
 rather than distributed maps in pipe_data.py

---
 src/soc/decoder/power_decoder2.py          | 11 ++++++++++-
 src/soc/decoder/power_regspec_map.py       | 11 +++++++----
 src/soc/fu/compunits/test/test_compunit.py |  4 +++-
 src/soc/fu/regspec.py                      | 10 ++++++++--
 4 files changed, 28 insertions(+), 8 deletions(-)

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 24d3e0c5..33e346ae 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -610,7 +610,16 @@ class PowerDecode2(Elaboratable):
         to Function Unit port regfiles (read-enable, read regnum, write regnum)
         regfile and regname arguments are fields 1 and 2 from a given regspec.
         """
-        return regspec_decode(self, regfile, regname)
+        return regspec_decode(self.e, regfile, regname)
+
+    def rdflags(self, cu):
+        rdl = []
+        for idx in range(cu.n_src):
+            regfile, regname, _ = cu.get_in_spec(idx)
+            rdflag, read, write = self.regspecmap(regfile, regname)
+            rdl.append(rdflag)
+        print ("rdflags", rdl)
+        return Cat(*rdl)
 
 
 if __name__ == '__main__':
diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py
index 6d9e1677..4e90b8db 100644
--- a/src/soc/decoder/power_regspec_map.py
+++ b/src/soc/decoder/power_regspec_map.py
@@ -70,11 +70,14 @@ def regspec_decode(e, regfile, name):
         CA = 1<<XERRegs.CA
         OV = 1<<XERRegs.OV
         if name == 'xer_so':
-            return e.oe.oe & e.oe.oe_ok, SO, SO
+            return Const(1), SO, SO # TODO
+            #return e.oe.oe & e.oe.oe_ok, SO, SO
         if name == 'xer_ov':
+            return Const(1), OV, OV # TODO
             return e.oe.oe & e.oe.oe_ok, OV, OV
         if name == 'xer_ca':
-            return e.input_carry, CA, CA
+            return Const(1), CA, CA # TODO
+            #return e.input_carry, CA, CA
 
     if regfile == 'FAST':
         # FAST register numbering is *unary* encoded
@@ -91,9 +94,9 @@ def regspec_decode(e, regfile, name):
             return Const(1), MSR, MS # TODO: detect read-conditions
         # TODO: remap the SPR numbers to FAST regs
         if name == 'spr1':
-            return e.read_spr1.ok, 1<<e.read_spr1.data, 1<<e.write_fast1.data
+            return e.read_fast1.ok, 1<<e.read_fast1.data, 1<<e.write_fast1.data
         if name == 'spr2':
-            return e.read_spr2.ok, 1<<e.read_spr2.data, 1<<e.write_fast2.data
+            return e.read_fast2.ok, 1<<e.read_fast2.data, 1<<e.write_fast2.data
 
     if regfile == 'SPR':
         assert False, "regfile TODO %s %s %d" % (refgile, repr(regspec), idx)
diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index eb419abd..ff884201 100644
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -153,7 +153,9 @@ class TestRunner(FHDLTestCase):
                     inp = get_inp_indexed(cu, iname)
 
                     # reset read-operand mask
-                    rdmask = cu.rdflags(pdecode2.e)
+                    rdmask = pdecode2.rdflags(cu)
+                    #print ("hardcoded rdmask", cu.rdflags(pdecode2.e))
+                    #print ("decoder rdmask", rdmask)
                     yield cu.rdmaskn.eq(~rdmask)
 
                     # reset write-operand mask
diff --git a/src/soc/fu/regspec.py b/src/soc/fu/regspec.py
index 1eedc303..18b16f38 100644
--- a/src/soc/fu/regspec.py
+++ b/src/soc/fu/regspec.py
@@ -66,11 +66,17 @@ class RegSpecALUAPI:
         self.rwid = rwid
         self.alu = alu # actual ALU - set as a "submodule" of the CU
 
+    def get_in_spec(self, i):
+        return self.rwid[0][i]
+
+    def get_out_spec(self, i):
+        return self.rwid[1][i]
+
     def get_in_name(self, i):
-        return self.rwid[0][i][1]
+        return self.get_in_spec(i)[1]
 
     def get_out_name(self, i):
-        return self.rwid[1][i][1]
+        return self.get_out_spec(i)[1]
 
     def get_out(self, i):
         if isinstance(self.rwid, int): # old - testing - API (rwid is int)
-- 
2.30.2