From 6fec3d2a952e460aa9fb94ed3eb05360aa7051a1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 25 Jul 2020 12:54:49 +0100 Subject: [PATCH] going on a bit of a "naming" spree, this for Jean-Paul to be able to identify operand records on pipelines --- src/soc/experiment/compalu_multi.py | 20 +++++++++++--------- src/soc/experiment/compldst_multi.py | 4 ++-- src/soc/fu/base_input_record.py | 6 ++++++ src/soc/fu/compunits/compunits.py | 3 ++- src/soc/fu/pipe_data.py | 2 +- 5 files changed, 22 insertions(+), 13 deletions(-) diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index 4565f2f3..acb7f3a6 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -57,7 +57,8 @@ class CompUnitRecord(RegSpec, RecordObject): def __init__(self, subkls, rwid, n_src=None, n_dst=None, name=None): RegSpec.__init__(self, rwid, n_src, n_dst) - RecordObject.__init__(self, name) + print ("name", name) + RecordObject.__init__(self) self._subkls = subkls n_src, n_dst = self._n_src, self._n_dst @@ -65,10 +66,10 @@ class CompUnitRecord(RegSpec, RecordObject): src = [] for i in range(n_src): j = i + 1 # name numbering to match src1/src2 - name = "src%d_i" % j + sname = "src%d_i" % j rw = self._get_srcwid(i) - sreg = Signal(rw, name=name, reset_less=True) - setattr(self, name, sreg) + sreg = Signal(rw, name=sname, reset_less=True) + setattr(self, sname, sreg) src.append(sreg) self._src_i = src @@ -76,16 +77,16 @@ class CompUnitRecord(RegSpec, RecordObject): dst = [] for i in range(n_dst): j = i + 1 # name numbering to match dest1/2... - name = "dest%d_o" % j + dname = "dest%d_o" % j rw = self._get_dstwid(i) # dreg = Data(rw, name=name) XXX ??? output needs to be a Data type? - dreg = Signal(rw, name=name, reset_less=True) - setattr(self, name, dreg) + dreg = Signal(rw, name=dname, reset_less=True) + setattr(self, dname, dreg) dst.append(dreg) self._dest = dst # operation / data input - self.oper_i = subkls(name="oper_i") # operand + self.oper_i = subkls(name="oper_i_%s" % name) # operand # create read/write and other scoreboard signalling self.rd = go_record(n_src, name="rd") # read in, req out @@ -114,7 +115,8 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): RegSpecALUAPI.__init__(self, rwid, alu) self.alu_name = name or "alu" self.opsubsetkls = opsubsetkls - self.cu = cu = CompUnitRecord(opsubsetkls, rwid, n_src, n_dst) + self.cu = cu = CompUnitRecord(opsubsetkls, rwid, n_src, n_dst, + name=name) n_src, n_dst = self.n_src, self.n_dst = cu._n_src, cu._n_dst print("n_src %d n_dst %d" % (self.n_src, self.n_dst)) diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py index c23d7131..4cce7c2c 100644 --- a/src/soc/experiment/compldst_multi.py +++ b/src/soc/experiment/compldst_multi.py @@ -171,11 +171,11 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable): """ def __init__(self, pi=None, rwid=64, awid=48, opsubset=CompLDSTOpSubset, - debugtest=False): + debugtest=False, name=None): super().__init__(rwid) self.awid = awid self.pi = pi - self.cu = cu = LDSTCompUnitRecord(rwid, opsubset) + self.cu = cu = LDSTCompUnitRecord(rwid, opsubset, name=name) self.debugtest = debugtest # POWER-compliant LD/ST has index and update: *fixed* number of ports diff --git a/src/soc/fu/base_input_record.py b/src/soc/fu/base_input_record.py index 2b37664f..db85ca9e 100644 --- a/src/soc/fu/base_input_record.py +++ b/src/soc/fu/base_input_record.py @@ -8,6 +8,12 @@ class CompOpSubsetBase(Record): base class of subset Operation information """ def __init__(self, layout, name): + if name is None: + name = self.__class__.__name__ + print ("Subset name", name) + assert name.startswith("Comp") + assert name.endswith("OpSubset") + name = name[4:-8].lower() + "_op" Record.__init__(self, Layout(layout), name=name) diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py index 455359f5..e790c14c 100644 --- a/src/soc/fu/compunits/compunits.py +++ b/src/soc/fu/compunits/compunits.py @@ -192,10 +192,11 @@ class LDSTFunctionUnit(LDSTCompUnit): fnunit = Function.LDST def __init__(self, pi, awid, idx): + alu_name = "ldst_%s%d" % (self.fnunit.name.lower(), idx) pspec = LDSTPipeSpec(id_wid=2) # spec (NNNPipeSpec instance) opsubset = pspec.opsubsetkls # get the operand subset class regspec = pspec.regspec # get the regspec - super().__init__(pi, regspec, awid, opsubset) + super().__init__(pi, regspec, awid, opsubset, name=alu_name) ##################################################################### diff --git a/src/soc/fu/pipe_data.py b/src/soc/fu/pipe_data.py index bdd22019..e944e868 100644 --- a/src/soc/fu/pipe_data.py +++ b/src/soc/fu/pipe_data.py @@ -67,6 +67,6 @@ class CommonPipeSpec: def __init__(self, id_wid): self.pipekls = SimpleHandshakeRedir self.id_wid = id_wid - self.opkls = lambda _: self.opsubsetkls(name="op") + self.opkls = lambda _: self.opsubsetkls() self.op_wid = get_rec_width(self.opkls(None)) # hmm.. self.stage = None -- 2.30.2