From 7043e6a5f345bebe98a7d7da92c1b3076bd1b05c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 1 Oct 2014 10:06:59 +0200 Subject: [PATCH] mila: simplify export --- miscope/mila.py | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/miscope/mila.py b/miscope/mila.py index a77d051c..b11c71e9 100644 --- a/miscope/mila.py +++ b/miscope/mila.py @@ -1,10 +1,13 @@ from migen.fhdl.structure import * +from migen.fhdl import verilog from migen.bank.description import * from miscope.std import * from miscope.trigger import Trigger from miscope.storage import Recorder, RunLengthEncoder +from mibuild.tools import write_to_file + class MiLa(Module, AutoCSR): def __init__(self, width, depth, ports, with_rle=False): self.width = width @@ -32,7 +35,8 @@ class MiLa(Module, AutoCSR): else: self.sink.connect(recorder.dat_sink) - def get_csv(self, layout, ns): + def export(self, design, layout, filename): + ret, ns = verilog.convert(design, return_ns=True) r = "" def format_line(*args): return ",".join(args) + "\n" @@ -43,4 +47,4 @@ class MiLa(Module, AutoCSR): for e in layout: r += format_line("layout", ns.get_name(e), str(flen(e))) - return r + write_to_file(filename, r) -- 2.30.2