From 7051c725ab9c8300fe4be7b8abcaf9da431606c2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 13 Jul 2020 13:03:28 +0100 Subject: [PATCH] add regression test, simulator is wrong --- src/soc/fu/shift_rot/test/test_pipe_caller.py | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py index 9c5701ee..5a56f017 100644 --- a/src/soc/fu/shift_rot/test/test_pipe_caller.py +++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py @@ -141,7 +141,14 @@ class ShiftRotTestCase(FHDLTestCase): initial_regs[1] = random.randint(0, (1<<64)-1) self.run_tst_program(Program(lst, bigendian), initial_regs) - def test_extswsli(self): + def test_regression_extswsli(self): + sh = random.randint(0, 63) + lst = [f"extswsli 3, 1, 34"] + initial_regs = [0] * 32 + initial_regs[1] = 0x5678 + self.run_tst_program(Program(lst, bigendian), initial_regs) + + def tst_extswsli(self): for i in range(40): sh = random.randint(0, 63) lst = [f"extswsli 3, 1, {sh}"] -- 2.30.2