From 705561c22923b4f1a1af70541fecd19cc90462a2 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Sun, 3 Apr 2022 10:38:15 +0200 Subject: [PATCH] backport wishbone_bram_wrapper changes --- wishbone_bram_wrapper.vhdl | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/wishbone_bram_wrapper.vhdl b/wishbone_bram_wrapper.vhdl index 51a4467..9a0358b 100644 --- a/wishbone_bram_wrapper.vhdl +++ b/wishbone_bram_wrapper.vhdl @@ -7,6 +7,8 @@ library work; use work.utils.all; use work.wishbone_types.all; +--- verilator access TODO + --! @brief Simple memory module for use in Wishbone-based systems. entity wishbone_bram_wrapper is generic( @@ -26,15 +28,15 @@ entity wishbone_bram_wrapper is bram_we : out std_ulogic; bram_re : out std_ulogic; bram_addr : out std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0); - bram_di : inout std_logic_vector(63 downto 0); - bram_do : out std_logic_vector(63 downto 0); + bram_di : out std_logic_vector(63 downto 0); + bram_do : in std_logic_vector(63 downto 0); bram_sel : out std_logic_vector(7 downto 0) ); end entity wishbone_bram_wrapper; architecture behaviour of wishbone_bram_wrapper is - constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE-1) - 3; + constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3; -- RAM interface signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0); @@ -46,6 +48,7 @@ architecture behaviour of wishbone_bram_wrapper is begin -- Actual RAM template + sim_ram: if SIM_MAIN_BRAM = true generate ram_0: entity work.main_bram generic map( WIDTH => 64, @@ -62,6 +65,15 @@ begin re => ram_re, we => ram_we ); + end generate; + + -- Verilator access to bram signals + bram_sel <= wishbone_in.sel; + wishbone_out.dat <= bram_do; + bram_di <= wishbone_in.dat; + bram_addr <= ram_addr; + bram_we <= ram_we; + bram_re <= ram_re; -- Wishbone interface ram_addr <= wishbone_in.adr(ram_addr_bits - 1 downto 0); -- 2.30.2