From 7060c28edd16a871fe1f8edaa8e49083a39b7ee5 Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Thu, 25 Nov 2021 13:11:25 +0000 Subject: [PATCH] Fix building the AArch64 assembler and disassembler when assertions are disabled. PR 28614 * aarch64-asm.c: Replace assert(0) with real code. * aarch64-dis.c: Likewise. * aarch64-opc.c: Likewise. --- opcodes/ChangeLog | 7 +++++++ opcodes/aarch64-asm.c | 26 +++++++++++++------------- opcodes/aarch64-dis.c | 33 +++++++++++++++++---------------- opcodes/aarch64-opc.c | 11 ++++++++--- 4 files changed, 45 insertions(+), 32 deletions(-) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 0cd504575fd..1e605183bc4 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2021-11-25 Nick Clifton + + PR 28614 + * aarch64-asm.c: Replace assert(0) with real code. + * aarch64-dis.c: Likewise. + * aarch64-opc.c: Likewise. + 2021-11-25 Nick Clifton * po/fr.po; Updated French translation. diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index fd5412aa38b..9b66fd34c7e 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -147,7 +147,7 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info, insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H); break; default: - assert (0); + return false; } } else if (inst->opcode->iclass == cryptosm3) @@ -185,7 +185,7 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info, insert_field (FLD_H, code, reglane_index, 0); break; default: - assert (0); + return false; } } return true; @@ -229,7 +229,7 @@ aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED, case 2: value = 0xa; break; case 3: value = 0x6; break; case 4: value = 0x2; break; - default: assert (0); + default: return false; } break; case 2: @@ -242,7 +242,7 @@ aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED, value = 0x0; break; default: - assert (0); + return false; } insert_field (FLD_opcode, code, value, 0); @@ -315,7 +315,7 @@ aarch64_ins_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, opcodeh2 = 0x2; break; default: - assert (0); + return false; } insert_fields (code, QSsize, 0, 3, FLD_vldst_size, FLD_S, FLD_Q); gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field); @@ -605,7 +605,7 @@ aarch64_ins_ft (const aarch64_operand *self, const aarch64_opnd_info *info, case AARCH64_OPND_QLF_S_S: value = 0; break; case AARCH64_OPND_QLF_S_D: value = 1; break; case AARCH64_OPND_QLF_S_Q: value = 2; break; - default: assert (0); + default: return false; } insert_field (FLD_ldst_size, code, value, 0); } @@ -1372,7 +1372,7 @@ aarch64_ins_sme_za_hv_tiles (const aarch64_operand *self, fld_zan_imm = regno; break; default: - assert (0); + return false; } insert_field (self->fields[0], code, fld_size, 0); @@ -1446,7 +1446,7 @@ aarch64_ins_sme_sm_za (const aarch64_operand *self, else if (info->reg.regno == 'z') fld_crm = 0x04; /* SVCRZA. */ else - assert (0); + return false; insert_field (self->fields[0], code, fld_crm, 0); return true; @@ -1510,7 +1510,7 @@ aarch64_ins_sme_pred_reg_with_index (const aarch64_operand *self, fld_tshl = 0x0; break; default: - assert (0); + return false; } insert_field (self->fields[2], code, fld_i1, 0); @@ -1544,7 +1544,7 @@ encode_asimd_fcvt (aarch64_inst *inst) qualifier = inst->operands[0].qualifier; break; default: - assert (0); + return; } assert (qualifier == AARCH64_OPND_QLF_V_4S || qualifier == AARCH64_OPND_QLF_V_2D); @@ -1749,7 +1749,7 @@ do_special_encoding (struct aarch64_inst *inst) case AARCH64_OPND_QLF_S_S: value = 0; break; case AARCH64_OPND_QLF_S_D: value = 1; break; case AARCH64_OPND_QLF_S_H: value = 3; break; - default: assert (0); + default: return; } insert_field (FLD_type, &inst->value, value, 0); } @@ -2098,13 +2098,13 @@ convert_mov_to_movewide (aarch64_inst *inst) value = ~inst->operands[1].imm.value; break; default: - assert (0); + return; } inst->operands[1].type = AARCH64_OPND_HALF; is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W; if (! aarch64_wide_constant_p (value, is32, &shift_amount)) /* The constraint check should have guaranteed this wouldn't happen. */ - assert (0); + return; value >>= shift_amount; value &= 0xffff; inst->operands[1].imm.value = value; diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 809cf8de930..46d602de07f 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -754,7 +754,7 @@ aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break; /* per word */ case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break; /* per half */ case 1: gen_sub_field (FLD_cmode, 1, 0, &field); break; /* per byte */ - default: assert (0); return false; + default: return false; } /* 00: 0; 01: 8; 10:16; 11:24. */ info->shifter.amount = extract_field_2 (&field, code, 0) << 3; @@ -766,7 +766,6 @@ aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, info->shifter.amount = extract_field_2 (&field, code, 0) ? 16 : 8; break; default: - assert (0); return false; } @@ -908,7 +907,7 @@ decode_limm (uint32_t esize, aarch64_insn value, int64_t *result) case 32: imm = (imm << 32) | imm; /* Fall through. */ case 64: break; - default: assert (0); return 0; + default: return 0; } *result = imm & ~((uint64_t) -1 << (esize * 4) << (esize * 4)); @@ -1276,7 +1275,7 @@ aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_sys_regs_sr[]. */ value = value & ~(0x7); break; - default: assert (0); return false; + default: return false; } for (i = 0; sysins_ops[i].name != NULL; ++i) @@ -1813,7 +1812,7 @@ aarch64_ext_sme_za_hv_tiles (const aarch64_operand *self, info->za_tile_vector.index.imm = 0; break; default: - assert (0); + return false; } return true; @@ -1885,7 +1884,7 @@ aarch64_ext_sme_sm_za (const aarch64_operand *self, else if (fld_crm == 0x2) info->reg.regno = 'z'; else - assert (0); + return false; return true; } @@ -2204,7 +2203,6 @@ decode_asimd_fcvt (aarch64_inst *inst) inst->operands[0].qualifier = qualifier; break; default: - assert (0); return 0; } @@ -2915,12 +2913,16 @@ determine_disassembling_preference (struct aarch64_inst *inst, successfully converted to the form of ALIAS. */ if (convert_to_alias (©, alias) == 1) { - int res; aarch64_replace_opcode (©, alias); - res = aarch64_match_operands_constraint (©, NULL); - assert (res == 1); - DEBUG_TRACE ("succeed with %s via conversion", alias->name); - memcpy (inst, ©, sizeof (aarch64_inst)); + if (aarch64_match_operands_constraint (©, NULL) != 1) + { + DEBUG_TRACE ("FAILED with alias %s ", alias->name); + } + else + { + DEBUG_TRACE ("succeed with %s via conversion", alias->name); + memcpy (inst, ©, sizeof (aarch64_inst)); + } return; } } @@ -3408,13 +3410,12 @@ print_aarch64_insn (bfd_vma pc, const aarch64_inst *inst, mismatch_details, &insn_sequence); switch (result) { - case ERR_UND: - case ERR_UNP: - case ERR_NYI: - assert (0); case ERR_VFI: print_verifier_notes (mismatch_details, info); break; + case ERR_UND: + case ERR_UNP: + case ERR_NYI: default: break; } diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index a37b3ffdd6d..ef0ba8a68f4 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3595,7 +3595,9 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64, opnd->imm.value, opnd->imm.value); break; - default: assert (0); + default: + snprintf (buf, size, ""); + break; } break; @@ -3662,7 +3664,9 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, snprintf (buf, size, "#%.18e", c.d); } break; - default: assert (0); + default: + snprintf (buf, size, ""); + break; } break; @@ -3934,7 +3938,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, break; default: - assert (0); + snprintf (buf, size, ""); + break; } } -- 2.30.2