From 70792a5b202a28869accc23c73ea6e260363cfb2 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 20 Nov 2023 15:03:10 +0000
Subject: [PATCH] sum RA+RB<<sh not RA<<sh+RB
 https://bugs.libre-soc.org/show_bug.cgi?id=1055

---
 openpower/isa/pifixedloadshift.mdwn | 22 ++++++++++++----------
 1 file changed, 12 insertions(+), 10 deletions(-)

diff --git a/openpower/isa/pifixedloadshift.mdwn b/openpower/isa/pifixedloadshift.mdwn
index 75a9a25b..e4eadda8 100644
--- a/openpower/isa/pifixedloadshift.mdwn
+++ b/openpower/isa/pifixedloadshift.mdwn
@@ -131,19 +131,21 @@ X-Form
 
 Pseudo-code:
 
-    EA <- (RA)<<(SH+1)
+    EA <- (RA)
     RT <- EXTS(MEM(EA, 4))
-    RA <- (RA) + (RB)
+    RA <- (RA) + (RB)<<(SH+1)
 
 Description:
 
-    Let the effective address (EA) be the contents of
-    register RA shifted by (SH+1).
+    Let the effective address (EA) be 
+    register RA 
 
     The word in storage addressed by EA is loaded into RT[32:63].
     RT[0:31] are filled with a copy of bit 0 of the loaded word.
 
-    The sum (RA) + (RB) is placed into register RA.
+    The contents of register RB shifted by (SH+1), summed with the
+    contents of register RA, is placed into register RA.
+
 
     If RA=0 or RA=RT, the instruction form is invalid.
 
@@ -159,18 +161,18 @@ X-Form
 
 Pseudo-code:
 
-    EA <- (RA)<<(SH+1)
+    EA <- (RA)
     RT <- MEM(EA, 8)
-    RA <- (RA) + (RB)
+    RA <- (RA) + (RB)<<(SH+1)
 
 Description:
 
-    Let the effective address (EA) be the contents of
-    register RA shifted by (SH+1).
+    Let the effective address (EA) be the contents of register RA.
 
     The doubleword in storage addressed by EA is loaded into RT.
 
-    The sum (RA) + (RB) is placed into register RA.
+    The contents of register RB shifted by (SH+1), summed with the
+    contents of register RA, is placed into register RA.
 
     If RA=0 or RA=RT, the instruction form is invalid.
 
-- 
2.30.2