From 707df19451f38cc9f69c019ec08ea38b8222b4da Mon Sep 17 00:00:00 2001 From: =?utf8?q?Nicolai=20H=C3=A4hnle?= Date: Wed, 3 May 2017 11:34:33 +0200 Subject: [PATCH] radeonsi: clarify documentation of existing SI workaround MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Limiting LS-HS to a single wave is required on all SI chips due to an issue with a power management feature. Reviewed-by: Marek Olšák --- src/gallium/drivers/radeonsi/si_state_draw.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index f0ed898cfb0..f7190055e3b 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -184,8 +184,10 @@ static void si_emit_derived_tess_state(struct si_context *sctx, */ *num_patches = MIN2(*num_patches, 40); - /* SI bug workaround - limit LS-HS threadgroups to only one wave. */ if (sctx->b.chip_class == SI) { + /* SI bug workaround, related to power management. Limit LS-HS + * threadgroups to only one wave. + */ unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp); *num_patches = MIN2(*num_patches, one_wave); -- 2.30.2