From 70a3113490cd5d3bbac37c394322e94ec3c55219 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 12 May 2021 15:33:04 +0100 Subject: [PATCH] add debug info, update comments, disable dcache in test all tracking down bugs in test_ldst_pi.py --- src/soc/experiment/test/test_ldst_pi.py | 1 + src/soc/experiment/test/test_mmu_dcache_pi.py | 4 ++-- src/soc/fu/ldst/loadstore.py | 3 +++ 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/soc/experiment/test/test_ldst_pi.py b/src/soc/experiment/test/test_ldst_pi.py index 82f56482..cd9a6773 100644 --- a/src/soc/experiment/test/test_ldst_pi.py +++ b/src/soc/experiment/test/test_ldst_pi.py @@ -138,6 +138,7 @@ def test_mmu(): pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb', imem_ifacetype='', + disable_cache=True, addr_wid=48, mask_wid=8, reg_wid=64) diff --git a/src/soc/experiment/test/test_mmu_dcache_pi.py b/src/soc/experiment/test/test_mmu_dcache_pi.py index a19d9cc5..35d58081 100644 --- a/src/soc/experiment/test/test_mmu_dcache_pi.py +++ b/src/soc/experiment/test/test_mmu_dcache_pi.py @@ -1,7 +1,7 @@ """MMU PortInterface Test -quite basic, goes directly to the MMU to assert signals (does not -yet use PortInterface) +quite basic, calls pi_ld to get data via PortInterface. this test +shouldn't really exist, it's superceded by test_ldst_pi.py """ from nmigen import (C, Module, Signal, Elaboratable, Mux, Cat, Repl, Signal) diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py index e5815b16..23d8fa4f 100644 --- a/src/soc/fu/ldst/loadstore.py +++ b/src/soc/fu/ldst/loadstore.py @@ -30,6 +30,7 @@ from soc.experiment.mem_types import MMUToLoadStore1Type from soc.minerva.wishbone import make_wb_layout from soc.bus.sram import SRAM +from nmutil.util import Display @unique @@ -212,11 +213,13 @@ class LoadStore1(PortInterfaceBase): with m.Case(State.MMU_LOOKUP): with m.If(m_in.done): with m.If(~self.instr_fault): + sync += Display("MMU_LOOKUP, done %x", self.addr) # retry the request now that the MMU has # installed a TLB entry m.d.comb += self.d_validblip.eq(1) # re-run dcache req sync += self.state.eq(State.ACK_WAIT) with m.Else(): + sync += Display("MMU_LOOKUP, exception %x", self.addr) # instruction lookup fault: store address in DAR comb += exc.happened.eq(1) sync += self.dar.eq(self.addr) -- 2.30.2