From 70eae5cbf9faf9df5832f39cae455087aceed7b7 Mon Sep 17 00:00:00 2001 From: Gabriel Somlo Date: Mon, 3 Aug 2020 14:32:26 -0400 Subject: [PATCH] interconnect/wishbone: increase WB address width to 31 This is needed to support memory regions up to 4GB in size (currently limited to 2GB, or 0x8000_0000). FIXME: CI complains about assertions re. axi_lite.address_width in relationship to len(wishbone.adr) and wishbone_adr_shift, which seems to be a problem on the 32bit (vexriscv?) CPU used for CI, but seems to work fine on Rocket. Signed-off-by: Gabriel Somlo foo --- litex/soc/interconnect/wishbone.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index d61edbea..235e14a3 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -35,7 +35,7 @@ _layout = [ class Interface(Record): - def __init__(self, data_width=32, adr_width=30): + def __init__(self, data_width=32, adr_width=31): self.data_width = data_width self.adr_width = adr_width Record.__init__(self, set_layout_parameters(_layout, -- 2.30.2