From 70edd30f0a5783356fb119cdaa990f14f3884bbc Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 9 Oct 2022 20:52:06 +0100 Subject: [PATCH] --- openpower/sv/rfc/ls002/discussion.mdwn | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/openpower/sv/rfc/ls002/discussion.mdwn b/openpower/sv/rfc/ls002/discussion.mdwn index 247fdf7f4..28e512ff2 100644 --- a/openpower/sv/rfc/ls002/discussion.mdwn +++ b/openpower/sv/rfc/ls002/discussion.mdwn @@ -40,7 +40,8 @@ be a different matter. architecture spec. In particular, the architecture spec tends to use "Move" for instructions that transfer data between registers. Here are two approaches. - +** +``` a. Model the instructions on li (Load Immediate), an extended mnemonic for addi. fmvis --> Floating Load Immediate Single (flis) @@ -58,7 +59,7 @@ be a different matter. I prefer (a), because I think it's confusing to treat these instructions, which don't access storage, like instructions that do access storage. -** +``` the fact that they bypass D-Cache and correspondingly raise no flags or exceptions is the connection to `ld`. despite that i like (a) as well -- 2.30.2