From 71018f77f21189ffc7137bf0567059f6889fb1a0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 14 Aug 2020 12:59:01 +0100 Subject: [PATCH] put multi-ports back (for read) on int and fast regfiles --- src/soc/regfile/regfiles.py | 8 +++++--- src/soc/simple/core.py | 18 ++++++++++-------- src/soc/simple/issuer_verilog.py | 7 +++++-- 3 files changed, 20 insertions(+), 13 deletions(-) diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py index 88b23209..58211449 100644 --- a/src/soc/regfile/regfiles.py +++ b/src/soc/regfile/regfiles.py @@ -69,8 +69,9 @@ class IntRegs(RegFileMem): #class IntRegs(RegFileArray): self.w_ports = {'o': self.write_port("dest1"), #'o1': self.write_port("dest2") # for now (LD/ST update) } - self.r_ports = {'rabc': self.read_port("src1"), - #'rbc': self.read_port("src3"), + self.r_ports = {'ra': self.read_port("src1"), + 'rb': self.read_port("src2"), + 'rc': self.read_port("src3"), 'dmi': self.read_port("dmi")} # needed for Debug (DMI) @@ -92,9 +93,10 @@ class FastRegs(RegFileMem): #RegFileArray): SRR1 = 4 def __init__(self): super().__init__(64, 5) - self.w_ports = {'fast1': self.write_port("dest3"), + self.w_ports = {'fast1': self.write_port("dest1"), } self.r_ports = {'fast1': self.read_port("src1"), + 'fast2': self.read_port("src2"), } diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index 117a937d..e5b03ffc 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -282,13 +282,14 @@ class NonProductionCore(Elaboratable): # argh. an experiment to merge RA and RB in the INT regfile # (we have too many read/write ports) - if regfile == 'INT': - fuspecs['rabc'] = [fuspecs.pop('rb')] - fuspecs['rabc'].append(fuspecs.pop('rc')) - fuspecs['rabc'].append(fuspecs.pop('ra')) - if regfile == 'FAST': - fuspecs['fast1'] = [fuspecs.pop('fast1')] - fuspecs['fast1'].append(fuspecs.pop('fast2')) + #if regfile == 'INT': + #fuspecs['rabc'] = [fuspecs.pop('rb')] + #fuspecs['rabc'].append(fuspecs.pop('rc')) + #fuspecs['rabc'].append(fuspecs.pop('ra')) + #if regfile == 'FAST': + # fuspecs['fast1'] = [fuspecs.pop('fast1')] + # if 'fast2' in fuspecs: + # fuspecs['fast1'].append(fuspecs.pop('fast2')) # for each named regfile port, connect up all FUs to that port for (regname, fspec) in sort_fuspecs(fuspecs): @@ -412,7 +413,8 @@ class NonProductionCore(Elaboratable): fuspecs['o'].append(fuspecs.pop('o1')) if regfile == 'FAST': fuspecs['fast1'] = [fuspecs.pop('fast1')] - fuspecs['fast1'].append(fuspecs.pop('fast2')) + if 'fast2' in fuspecs: + fuspecs['fast1'].append(fuspecs.pop('fast2')) for (regname, fspec) in sort_fuspecs(fuspecs): self.connect_wrport(m, fu_bitdict, wrpickers, diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py index 90b83081..9ba52fe6 100644 --- a/src/soc/simple/issuer_verilog.py +++ b/src/soc/simple/issuer_verilog.py @@ -9,11 +9,14 @@ from soc.simple.issuer import TestIssuer if __name__ == '__main__': - units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1, + units = {'alu': 1, + 'cr': 1, 'branch': 1, 'trap': 1, + 'logical': 1, 'spr': 1, 'div': 1, 'mul': 1, - 'shiftrot': 1} + 'shiftrot': 1 + } pspec = TestMemPspec(ldst_ifacetype='bare_wb', imem_ifacetype='bare_wb', addr_wid=48, -- 2.30.2