From 711540e15c4855487f126958b43e8f27d560f207 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 21 Mar 2015 18:10:56 +0100 Subject: [PATCH] targets/mlabs_video: rename sdram_module to sdram_modules to reflect that we have 2 modules sharing the same characteristics --- targets/mlabs_video.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index ddd24380..da8c99d6 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -42,7 +42,7 @@ class BaseSoC(SDRAMSoC): self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq) if not self.with_main_ram: - sdram_module = MT46V32M16(self.clk_freq) + sdram_modules = MT46V32M16(self.clk_freq) sdram_controller_settings = sdram.ControllerSettings( req_queue_size=8, read_time=32, @@ -50,7 +50,7 @@ class BaseSoC(SDRAMSoC): ) self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR", rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1") - self.register_sdram_phy(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings, + self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings, sdram_controller_settings) -- 2.30.2