From 7177e259c1b37c971992402a1e394041a4c44252 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 7 Apr 2022 11:50:14 +0100 Subject: [PATCH] --- openpower/sv/branches.mdwn | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn index 3ee7c38ed..732c6c980 100644 --- a/openpower/sv/branches.mdwn +++ b/openpower/sv/branches.mdwn @@ -322,6 +322,16 @@ acting in effect as either a popcount or cntlz depending on which mode bits are set. In short, Vectorised Branch becomes an extremely powerful tool. +* **Micro-Architectural Implementation Note**: when implemented on +top of a Multi-Issue Out-of-Order Engine it is possible to pass +a copy of the predicate and the prerequisite CR Fields to all +Branch Units, as well as the current value of CTR at the time of +multi-issue, and for each Branch Unit to compute how many times +CTR would be subtracted, in a fully-deterministic and parallel +fashion. A SIMD-based Branch Unit, receiving and processing +multiple CR Fields covered by multiple predicate bits, would +do the exact same thing.* + ## CTR-test Where a standard Scalar v3.0B branch unconditionally decrements @@ -357,7 +367,7 @@ a predicate mask bit is clear. **All** other SVP64 operations entirely skip an element when sz=0 and a predicate mask bit is zero. It is also critical to emphasise that in this unusual mode, no other side-effects occur: **only** CTR is decremented, i.e. the -rest of the Branch operation iss skipped. +rest of the Branch operation is skipped. # VLSET Mode -- 2.30.2