From 7191dd16f9d486fbe107b2c24d1858c8f88329b3 Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 18 Jun 2020 23:34:52 +0000 Subject: [PATCH] Use C++11 final/override keywords. --- backends/aiger/aiger.cc | 4 ++-- backends/aiger/xaiger.cc | 4 ++-- backends/blif/blif.cc | 4 ++-- backends/btor/btor.cc | 4 ++-- backends/cxxrtl/cxxrtl_backend.cc | 4 ++-- backends/edif/edif.cc | 4 ++-- backends/firrtl/firrtl.cc | 4 ++-- backends/ilang/ilang_backend.cc | 8 ++++---- backends/intersynth/intersynth.cc | 4 ++-- backends/json/json.cc | 8 ++++---- backends/protobuf/protobuf.cc | 8 ++++---- backends/simplec/simplec.cc | 4 ++-- backends/smt2/smt2.cc | 4 ++-- backends/smv/smv.cc | 4 ++-- backends/spice/spice.cc | 4 ++-- backends/table/table.cc | 4 ++-- backends/verilog/verilog_backend.cc | 4 ++-- examples/cxx-api/evaldemo.cc | 2 +- frontends/aiger/aigerparse.cc | 4 ++-- frontends/ast/ast.h | 10 +++++----- frontends/blif/blifparse.cc | 4 ++-- frontends/ilang/ilang_frontend.cc | 4 ++-- frontends/json/jsonparse.cc | 4 ++-- frontends/liberty/liberty.cc | 4 ++-- frontends/rpc/rpc_frontend.cc | 16 ++++++++-------- frontends/verific/verific.cc | 10 +++++----- frontends/verilog/verilog_frontend.cc | 12 ++++++------ kernel/celledges.h | 4 ++-- kernel/modtools.h | 8 ++++---- kernel/register.cc | 10 +++++----- kernel/register.h | 12 ++++++------ kernel/yosys.cc | 16 ++++++++-------- kernel/yosys.h | 8 -------- manual/CHAPTER_Prog/stubnets.cc | 2 +- manual/PRESENTATION_Prog/my_cmd.cc | 6 +++--- passes/cmds/add.cc | 4 ++-- passes/cmds/autoname.cc | 4 ++-- passes/cmds/blackbox.cc | 4 ++-- passes/cmds/bugpoint.cc | 4 ++-- passes/cmds/check.cc | 4 ++-- passes/cmds/chformal.cc | 4 ++-- passes/cmds/chtype.cc | 4 ++-- passes/cmds/connect.cc | 4 ++-- passes/cmds/connwrappers.cc | 4 ++-- passes/cmds/copy.cc | 4 ++-- passes/cmds/cover.cc | 4 ++-- passes/cmds/delete.cc | 4 ++-- passes/cmds/design.cc | 6 +++--- passes/cmds/edgetypes.cc | 4 ++-- passes/cmds/exec.cc | 4 ++-- passes/cmds/logcmd.cc | 4 ++-- passes/cmds/logger.cc | 4 ++-- passes/cmds/ltp.cc | 4 ++-- passes/cmds/plugin.cc | 4 ++-- passes/cmds/portlist.cc | 4 ++-- passes/cmds/printattrs.cc | 4 ++-- passes/cmds/qwp.cc | 4 ++-- passes/cmds/rename.cc | 4 ++-- passes/cmds/scatter.cc | 4 ++-- passes/cmds/scc.cc | 4 ++-- passes/cmds/scratchpad.cc | 4 ++-- passes/cmds/select.cc | 12 ++++++------ passes/cmds/setattr.cc | 16 ++++++++-------- passes/cmds/setundef.cc | 4 ++-- passes/cmds/show.cc | 4 ++-- passes/cmds/splice.cc | 4 ++-- passes/cmds/splitnets.cc | 4 ++-- passes/cmds/stat.cc | 4 ++-- passes/cmds/tee.cc | 4 ++-- passes/cmds/torder.cc | 4 ++-- passes/cmds/trace.cc | 20 ++++++++++---------- passes/cmds/write_file.cc | 4 ++-- passes/equiv/equiv_add.cc | 4 ++-- passes/equiv/equiv_induct.cc | 4 ++-- passes/equiv/equiv_make.cc | 4 ++-- passes/equiv/equiv_mark.cc | 4 ++-- passes/equiv/equiv_miter.cc | 4 ++-- passes/equiv/equiv_opt.cc | 8 ++++---- passes/equiv/equiv_purge.cc | 4 ++-- passes/equiv/equiv_remove.cc | 4 ++-- passes/equiv/equiv_simple.cc | 4 ++-- passes/equiv/equiv_status.cc | 4 ++-- passes/equiv/equiv_struct.cc | 4 ++-- passes/fsm/fsm.cc | 4 ++-- passes/fsm/fsm_detect.cc | 4 ++-- passes/fsm/fsm_expand.cc | 4 ++-- passes/fsm/fsm_export.cc | 4 ++-- passes/fsm/fsm_extract.cc | 4 ++-- passes/fsm/fsm_info.cc | 4 ++-- passes/fsm/fsm_map.cc | 4 ++-- passes/fsm/fsm_opt.cc | 4 ++-- passes/fsm/fsm_recode.cc | 4 ++-- passes/hierarchy/hierarchy.cc | 4 ++-- passes/hierarchy/submod.cc | 4 ++-- passes/hierarchy/uniquify.cc | 4 ++-- passes/memory/memory.cc | 4 ++-- passes/memory/memory_bram.cc | 4 ++-- passes/memory/memory_collect.cc | 4 ++-- passes/memory/memory_dff.cc | 4 ++-- passes/memory/memory_map.cc | 4 ++-- passes/memory/memory_memx.cc | 4 ++-- passes/memory/memory_nordff.cc | 4 ++-- passes/memory/memory_share.cc | 4 ++-- passes/memory/memory_unpack.cc | 4 ++-- passes/opt/muxpack.cc | 4 ++-- passes/opt/opt.cc | 4 ++-- passes/opt/opt_clean.cc | 8 ++++---- passes/opt/opt_demorgan.cc | 4 ++-- passes/opt/opt_expr.cc | 4 ++-- passes/opt/opt_lut.cc | 4 ++-- passes/opt/opt_lut_ins.cc | 4 ++-- passes/opt/opt_mem.cc | 4 ++-- passes/opt/opt_merge.cc | 4 ++-- passes/opt/opt_muxtree.cc | 4 ++-- passes/opt/opt_reduce.cc | 4 ++-- passes/opt/opt_rmdff.cc | 4 ++-- passes/opt/opt_share.cc | 4 ++-- passes/opt/pmux2shiftx.cc | 8 ++++---- passes/opt/rmports.cc | 4 ++-- passes/opt/share.cc | 4 ++-- passes/opt/wreduce.cc | 4 ++-- passes/pmgen/ice40_dsp.cc | 4 ++-- passes/pmgen/ice40_wrapcarry.cc | 4 ++-- passes/pmgen/peepopt.cc | 4 ++-- passes/pmgen/test_pmgen.cc | 4 ++-- passes/pmgen/xilinx_dsp.cc | 4 ++-- passes/pmgen/xilinx_srl.cc | 4 ++-- passes/proc/proc.cc | 4 ++-- passes/proc/proc_arst.cc | 4 ++-- passes/proc/proc_clean.cc | 4 ++-- passes/proc/proc_dff.cc | 4 ++-- passes/proc/proc_dlatch.cc | 4 ++-- passes/proc/proc_init.cc | 4 ++-- passes/proc/proc_mux.cc | 4 ++-- passes/proc/proc_prune.cc | 4 ++-- passes/proc/proc_rmdead.cc | 4 ++-- passes/sat/assertpmux.cc | 4 ++-- passes/sat/async2sync.cc | 4 ++-- passes/sat/clk2fflogic.cc | 4 ++-- passes/sat/cutpoint.cc | 4 ++-- passes/sat/eval.cc | 4 ++-- passes/sat/expose.cc | 4 ++-- passes/sat/fmcombine.cc | 4 ++-- passes/sat/fminit.cc | 4 ++-- passes/sat/freduce.cc | 4 ++-- passes/sat/miter.cc | 4 ++-- passes/sat/mutate.cc | 4 ++-- passes/sat/qbfsat.cc | 4 ++-- passes/sat/sat.cc | 4 ++-- passes/sat/sim.cc | 4 ++-- passes/sat/supercover.cc | 4 ++-- passes/techmap/abc.cc | 4 ++-- passes/techmap/abc9.cc | 10 +++++----- passes/techmap/abc9_exe.cc | 4 ++-- passes/techmap/abc9_ops.cc | 4 ++-- passes/techmap/aigmap.cc | 4 ++-- passes/techmap/alumacc.cc | 4 ++-- passes/techmap/attrmap.cc | 16 ++++++++-------- passes/techmap/attrmvcp.cc | 4 ++-- passes/techmap/clkbufmap.cc | 4 ++-- passes/techmap/deminout.cc | 4 ++-- passes/techmap/dff2dffe.cc | 4 ++-- passes/techmap/dff2dffs.cc | 4 ++-- passes/techmap/dffinit.cc | 4 ++-- passes/techmap/dfflibmap.cc | 4 ++-- passes/techmap/extract.cc | 4 ++-- passes/techmap/extract_counter.cc | 4 ++-- passes/techmap/extract_fa.cc | 4 ++-- passes/techmap/extract_reduce.cc | 4 ++-- passes/techmap/extractinv.cc | 4 ++-- passes/techmap/flatten.cc | 4 ++-- passes/techmap/flowmap.cc | 4 ++-- passes/techmap/hilomap.cc | 4 ++-- passes/techmap/insbuf.cc | 4 ++-- passes/techmap/iopadmap.cc | 4 ++-- passes/techmap/lut2mux.cc | 4 ++-- passes/techmap/maccmap.cc | 4 ++-- passes/techmap/muxcover.cc | 4 ++-- passes/techmap/nlutmap.cc | 4 ++-- passes/techmap/pmuxtree.cc | 4 ++-- passes/techmap/shregmap.cc | 4 ++-- passes/techmap/simplemap.cc | 4 ++-- passes/techmap/techmap.cc | 4 ++-- passes/techmap/tribuf.cc | 4 ++-- passes/techmap/zinit.cc | 4 ++-- passes/tests/test_abcloop.cc | 4 ++-- passes/tests/test_autotb.cc | 4 ++-- passes/tests/test_cell.cc | 4 ++-- techlibs/achronix/synth_achronix.cc | 8 ++++---- techlibs/anlogic/anlogic_eqn.cc | 4 ++-- techlibs/anlogic/anlogic_fixcarry.cc | 4 ++-- techlibs/anlogic/synth_anlogic.cc | 8 ++++---- techlibs/common/prep.cc | 8 ++++---- techlibs/common/synth.cc | 8 ++++---- techlibs/coolrunner2/coolrunner2_fixup.cc | 4 ++-- techlibs/coolrunner2/coolrunner2_sop.cc | 4 ++-- techlibs/coolrunner2/synth_coolrunner2.cc | 8 ++++---- techlibs/easic/synth_easic.cc | 8 ++++---- techlibs/ecp5/ecp5_ffinit.cc | 4 ++-- techlibs/ecp5/ecp5_gsr.cc | 4 ++-- techlibs/ecp5/synth_ecp5.cc | 10 +++++----- techlibs/efinix/efinix_fixcarry.cc | 4 ++-- techlibs/efinix/efinix_gbuf.cc | 4 ++-- techlibs/efinix/synth_efinix.cc | 8 ++++---- techlibs/gowin/determine_init.cc | 4 ++-- techlibs/gowin/synth_gowin.cc | 8 ++++---- techlibs/greenpak4/greenpak4_dffinv.cc | 4 ++-- techlibs/greenpak4/synth_greenpak4.cc | 8 ++++---- techlibs/ice40/ice40_braminit.cc | 4 ++-- techlibs/ice40/ice40_ffinit.cc | 4 ++-- techlibs/ice40/ice40_ffssr.cc | 4 ++-- techlibs/ice40/ice40_opt.cc | 4 ++-- techlibs/ice40/synth_ice40.cc | 10 +++++----- techlibs/intel/synth_intel.cc | 8 ++++---- techlibs/intel_alm/synth_intel_alm.cc | 8 ++++---- techlibs/sf2/sf2_iobs.cc | 4 ++-- techlibs/sf2/synth_sf2.cc | 8 ++++---- techlibs/xilinx/synth_xilinx.cc | 10 +++++----- techlibs/xilinx/xilinx_dffopt.cc | 4 ++-- tests/various/plugin.cc | 2 +- 220 files changed, 540 insertions(+), 548 deletions(-) diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index e5a41b5c5..81a3f483b 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -681,7 +681,7 @@ struct AigerWriter struct AigerBackend : public Backend { AigerBackend() : Backend("aiger", "write design to AIGER file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -719,7 +719,7 @@ struct AigerBackend : public Backend { log(" AIGER file happy.\n"); log("\n"); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { bool ascii_mode = false; bool zinit_mode = false; diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 8bbadbc91..ef0103c17 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -731,7 +731,7 @@ struct XAigerWriter struct XAigerBackend : public Backend { XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -753,7 +753,7 @@ struct XAigerBackend : public Backend { log(" write $_DFF_[NP]_ cells\n"); log("\n"); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { bool ascii_mode = false, dff_mode = false; std::string map_filename; diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index b028df848..780a16320 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -482,7 +482,7 @@ struct BlifDumper struct BlifBackend : public Backend { BlifBackend() : Backend("blif", "write design to BLIF file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -552,7 +552,7 @@ struct BlifBackend : public Backend { log(" do not write definitions for the $true, $false and $undef wires.\n"); log("\n"); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { std::string top_module_name; std::string buf_type, buf_in, buf_out; diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 9ac312480..e5da6c1e7 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -1335,7 +1335,7 @@ struct BtorWorker struct BtorBackend : public Backend { BtorBackend() : Backend("btor", "write design to BTOR file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1359,7 +1359,7 @@ struct BtorBackend : public Backend { log(" Output symbols for internal netnames (starting with '$')\n"); log("\n"); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { bool verbose = false, single_bad = false, cover_mode = false, print_internal_names = false; string info_filename; diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index bd2666a78..1cb407a28 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -2313,7 +2313,7 @@ struct CxxrtlBackend : public Backend { static const int DEFAULT_DEBUG_LEVEL = 1; CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -2535,7 +2535,7 @@ struct CxxrtlBackend : public Backend { log("\n"); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { bool noflatten = false; bool noproc = false; diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 7e24468c0..5e6becfd0 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -90,7 +90,7 @@ struct EdifNames struct EdifBackend : public Backend { EdifBackend() : Backend("edif", "write design to EDIF netlist file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -126,7 +126,7 @@ struct EdifBackend : public Backend { log("is targeted.\n"); log("\n"); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { log_header(design, "Executing EDIF backend.\n"); std::string top_module_name; diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index b1d8500bb..9739a7a9f 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -1123,7 +1123,7 @@ struct FirrtlWorker struct FirrtlBackend : public Backend { FirrtlBackend() : Backend("firrtl", "write design to a FIRRTL file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1134,7 +1134,7 @@ struct FirrtlBackend : public Backend { log(" pmuxtree\n"); log("\n"); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { size_t argidx = args.size(); // We aren't expecting any arguments. diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc index 3a418de3c..cf0d3feca 100644 --- a/backends/ilang/ilang_backend.cc +++ b/backends/ilang/ilang_backend.cc @@ -400,7 +400,7 @@ PRIVATE_NAMESPACE_BEGIN struct IlangBackend : public Backend { IlangBackend() : Backend("ilang", "write design to ilang file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -413,7 +413,7 @@ struct IlangBackend : public Backend { log(" only write selected parts of the design.\n"); log("\n"); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { bool selected = false; @@ -440,7 +440,7 @@ struct IlangBackend : public Backend { struct DumpPass : public Pass { DumpPass() : Pass("dump", "print parts of the design in ilang format") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -463,7 +463,7 @@ struct DumpPass : public Pass { log(" like -outfile but append instead of overwrite\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::string filename; bool flag_m = false, flag_n = false, append = false; diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 31dce1cca..98a14173b 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -46,7 +46,7 @@ static std::string netname(std::set &conntypes_code, std::set args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { log_header(design, "Executing INTERSYNTH backend.\n"); log_push(); diff --git a/backends/json/json.cc b/backends/json/json.cc index 5edc50f60..eeadc1b89 100644 --- a/backends/json/json.cc +++ b/backends/json/json.cc @@ -294,7 +294,7 @@ struct JsonWriter struct JsonBackend : public Backend { JsonBackend() : Backend("json", "write design to a JSON file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -530,7 +530,7 @@ struct JsonBackend : public Backend { log("format. A program processing this format must ignore all unknown fields.\n"); log("\n"); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { bool aig_mode = false; bool compat_int_mode = false; @@ -559,7 +559,7 @@ struct JsonBackend : public Backend { struct JsonPass : public Pass { JsonPass() : Pass("json", "write design in JSON format") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -580,7 +580,7 @@ struct JsonPass : public Pass { log("See 'help write_json' for a description of the JSON format used.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::string filename; bool aig_mode = false; diff --git a/backends/protobuf/protobuf.cc b/backends/protobuf/protobuf.cc index 671686173..f6623a382 100644 --- a/backends/protobuf/protobuf.cc +++ b/backends/protobuf/protobuf.cc @@ -231,7 +231,7 @@ struct ProtobufDesignSerializer struct ProtobufBackend : public Backend { ProtobufBackend(): Backend("protobuf", "write design to a Protocol Buffer file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -249,7 +249,7 @@ struct ProtobufBackend : public Backend { log("Yosys source code distribution.\n"); log("\n"); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { bool aig_mode = false; bool text_mode = false; @@ -286,7 +286,7 @@ struct ProtobufBackend : public Backend { struct ProtobufPass : public Pass { ProtobufPass() : Pass("protobuf", "write design in Protobuf format") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -307,7 +307,7 @@ struct ProtobufPass : public Pass { log("Yosys source code distribution.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::string filename; bool aig_mode = false; diff --git a/backends/simplec/simplec.cc b/backends/simplec/simplec.cc index 83ed5e6e0..3adeaa6c0 100644 --- a/backends/simplec/simplec.cc +++ b/backends/simplec/simplec.cc @@ -744,7 +744,7 @@ struct SimplecWorker struct SimplecBackend : public Backend { SimplecBackend() : Backend("simplec", "convert design to simple C code") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -763,7 +763,7 @@ struct SimplecBackend : public Backend { log("THIS COMMAND IS UNDER CONSTRUCTION\n"); log("\n"); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { reserved_cids.clear(); id2cid.clear(); diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc index 26f17bcb3..526b36352 100644 --- a/backends/smt2/smt2.cc +++ b/backends/smt2/smt2.cc @@ -1280,7 +1280,7 @@ struct Smt2Worker struct Smt2Backend : public Backend { Smt2Backend() : Backend("smt2", "write design to SMT-LIBv2 file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1436,7 +1436,7 @@ struct Smt2Backend : public Backend { log("from non-zero to zero in the test design.\n"); log("\n"); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { std::ifstream template_f; bool bvmode = true, memmode = true, wiresmode = false, verbose = false, statebv = false, statedt = false; diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc index 2fc7099f4..4e5c6050d 100644 --- a/backends/smv/smv.cc +++ b/backends/smv/smv.cc @@ -702,7 +702,7 @@ struct SmvWorker struct SmvBackend : public Backend { SmvBackend() : Backend("smv", "write design to SMV file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -720,7 +720,7 @@ struct SmvBackend : public Backend { log("THIS COMMAND IS UNDER CONSTRUCTION\n"); log("\n"); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { std::ifstream template_f; bool verbose = false; diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc index 84e93b61b..aa20f106a 100644 --- a/backends/spice/spice.cc +++ b/backends/spice/spice.cc @@ -130,7 +130,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De struct SpiceBackend : public Backend { SpiceBackend() : Backend("spice", "write design to SPICE netlist file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -159,7 +159,7 @@ struct SpiceBackend : public Backend { log(" set the specified module as design top module\n"); log("\n"); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { std::string top_module_name; RTLIL::Module *top_module = NULL; diff --git a/backends/table/table.cc b/backends/table/table.cc index 796f18059..77642ccbd 100644 --- a/backends/table/table.cc +++ b/backends/table/table.cc @@ -29,7 +29,7 @@ PRIVATE_NAMESPACE_BEGIN struct TableBackend : public Backend { TableBackend() : Backend("table", "write design as connectivity table") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -48,7 +48,7 @@ struct TableBackend : public Backend { log("module inputs and outputs are output using cell type and port '-' and with\n"); log("'pi' (primary input) or 'po' (primary output) or 'pio' as direction.\n"); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { log_header(design, "Executing TABLE backend.\n"); diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 4f44a053a..cef1dd9df 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1873,7 +1873,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) struct VerilogBackend : public Backend { VerilogBackend() : Backend("verilog", "write design to Verilog file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1953,7 +1953,7 @@ struct VerilogBackend : public Backend { log("this command is called on a design with RTLIL processes.\n"); log("\n"); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { log_header(design, "Executing Verilog backend.\n"); diff --git a/examples/cxx-api/evaldemo.cc b/examples/cxx-api/evaldemo.cc index 756b7faac..cfe0c0804 100644 --- a/examples/cxx-api/evaldemo.cc +++ b/examples/cxx-api/evaldemo.cc @@ -22,7 +22,7 @@ struct EvalDemoPass : public Pass { EvalDemoPass() : Pass("evaldemo") { } - void execute(vector, Design *design) YS_OVERRIDE + void execute(vector, Design *design) override { Module *module = design->top_module(); diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index fef788267..9d967e6fc 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -970,7 +970,7 @@ void AigerReader::post_process() struct AigerFrontend : public Frontend { AigerFrontend() : Frontend("aiger", "read AIGER file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -996,7 +996,7 @@ struct AigerFrontend : public Frontend { log(" read XAIGER extensions\n"); log("\n"); } - void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { log_header(design, "Executing AIGER frontend.\n"); diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index b8f24ee14..46864a4e1 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -322,12 +322,12 @@ namespace AST struct AstModule : RTLIL::Module { AstNode *ast; bool nolatches, nomeminit, nomem2reg, mem2reg, noblackbox, lib, nowb, noopt, icells, pwires, autowire; - ~AstModule() YS_OVERRIDE; - RTLIL::IdString derive(RTLIL::Design *design, const dict ¶meters, bool mayfail) YS_OVERRIDE; - RTLIL::IdString derive(RTLIL::Design *design, const dict ¶meters, const dict &interfaces, const dict &modports, bool mayfail) YS_OVERRIDE; + ~AstModule() override; + RTLIL::IdString derive(RTLIL::Design *design, const dict ¶meters, bool mayfail) override; + RTLIL::IdString derive(RTLIL::Design *design, const dict ¶meters, const dict &interfaces, const dict &modports, bool mayfail) override; std::string derive_common(RTLIL::Design *design, const dict ¶meters, AstNode **new_ast_out, bool quiet = false); - void reprocess_module(RTLIL::Design *design, const dict &local_interfaces) YS_OVERRIDE; - RTLIL::Module *clone() const YS_OVERRIDE; + void reprocess_module(RTLIL::Design *design, const dict &local_interfaces) override; + RTLIL::Module *clone() const override; void loadconfig() const; }; diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index 7cc157e49..9ae3fac2c 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -586,7 +586,7 @@ error_with_reason: struct BlifFrontend : public Frontend { BlifFrontend() : Frontend("blif", "read BLIF file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -602,7 +602,7 @@ struct BlifFrontend : public Frontend { log(" multi-bit port 'name'.\n"); log("\n"); } - void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { bool sop_mode = false; bool wideports = false; diff --git a/frontends/ilang/ilang_frontend.cc b/frontends/ilang/ilang_frontend.cc index 30d9ff79d..973e62f2c 100644 --- a/frontends/ilang/ilang_frontend.cc +++ b/frontends/ilang/ilang_frontend.cc @@ -35,7 +35,7 @@ YOSYS_NAMESPACE_BEGIN struct IlangFrontend : public Frontend { IlangFrontend() : Frontend("ilang", "read modules from ilang file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -56,7 +56,7 @@ struct IlangFrontend : public Frontend { log(" only create empty blackbox modules\n"); log("\n"); } - void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { ILANG_FRONTEND::flag_nooverwrite = false; ILANG_FRONTEND::flag_overwrite = false; diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc index 8ae7c6578..1b34aaf3a 100644 --- a/frontends/json/jsonparse.cc +++ b/frontends/json/jsonparse.cc @@ -535,7 +535,7 @@ void json_import(Design *design, string &modname, JsonNode *node) struct JsonFrontend : public Frontend { JsonFrontend() : Frontend("json", "read JSON file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -545,7 +545,7 @@ struct JsonFrontend : public Frontend { log("for a description of the file format.\n"); log("\n"); } - void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { log_header(design, "Executing JSON frontend.\n"); diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc index 6f0c3fefa..f77d7da56 100644 --- a/frontends/liberty/liberty.cc +++ b/frontends/liberty/liberty.cc @@ -453,7 +453,7 @@ void parse_type_map(std::map> &type_map, struct LibertyFrontend : public Frontend { LibertyFrontend() : Frontend("liberty", "read cells from liberty file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -486,7 +486,7 @@ struct LibertyFrontend : public Frontend { log(" set the specified attribute (to the value 1) on all loaded modules\n"); log("\n"); } - void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { bool flag_lib = false; bool flag_nooverwrite = false; diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc index 46ee6a733..6d72cbff5 100644 --- a/frontends/rpc/rpc_frontend.cc +++ b/frontends/rpc/rpc_frontend.cc @@ -157,7 +157,7 @@ struct RpcServer { struct RpcModule : RTLIL::Module { std::shared_ptr server; - RTLIL::IdString derive(RTLIL::Design *design, const dict ¶meters, bool /*mayfail*/) YS_OVERRIDE { + RTLIL::IdString derive(RTLIL::Design *design, const dict ¶meters, bool /*mayfail*/) override { std::string stripped_name = name.str(); if (stripped_name.compare(0, 9, "$abstract") == 0) stripped_name = stripped_name.substr(9); @@ -229,7 +229,7 @@ struct RpcModule : RTLIL::Module { return derived_name; } - RTLIL::Module *clone() const YS_OVERRIDE { + RTLIL::Module *clone() const override { RpcModule *new_mod = new RpcModule; new_mod->server = server; cloneInto(new_mod); @@ -250,7 +250,7 @@ struct HandleRpcServer : RpcServer { HandleRpcServer(const std::string &name, HANDLE hsend, HANDLE hrecv) : RpcServer(name), hsend(hsend), hrecv(hrecv) { } - void write(const std::string &data) YS_OVERRIDE { + void write(const std::string &data) override { log_assert(data.length() >= 1 && data.find('\n') == data.length() - 1); ssize_t offset = 0; do { @@ -261,7 +261,7 @@ struct HandleRpcServer : RpcServer { } while(offset < (ssize_t)data.length()); } - std::string read() YS_OVERRIDE { + std::string read() override { std::string data; ssize_t offset = 0; while (data.length() == 0 || data[data.length() - 1] != '\n') { @@ -304,7 +304,7 @@ struct FdRpcServer : RpcServer { log_cmd_error("RPC frontend terminated unexpectedly\n"); } - void write(const std::string &data) YS_OVERRIDE { + void write(const std::string &data) override { log_assert(data.length() >= 1 && data.find('\n') == data.length() - 1); ssize_t offset = 0; do { @@ -316,7 +316,7 @@ struct FdRpcServer : RpcServer { } while(offset < (ssize_t)data.length()); } - std::string read() YS_OVERRIDE { + std::string read() override { std::string data; ssize_t offset = 0; while (data.length() == 0 || data[data.length() - 1] != '\n') { @@ -346,7 +346,7 @@ struct FdRpcServer : RpcServer { // RpcFrontend does not inherit from Frontend since it does not read files. struct RpcFrontend : public Pass { RpcFrontend() : Pass("connect_rpc", "connect to RPC frontend") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -390,7 +390,7 @@ struct RpcFrontend : public Pass { log(" so the response should be the same whenever the same set of parameters\n"); log(" is provided.\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Connecting to RPC frontend.\n"); diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index a22a8a93d..1630c57bc 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2008,7 +2008,7 @@ bool check_noverific_env() struct VerificPass : public Pass { VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -2147,7 +2147,7 @@ struct VerificPass : public Pass { log("\n"); } #ifdef YOSYS_ENABLE_VERIFIC - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { static bool set_verific_global_flags = true; @@ -2582,7 +2582,7 @@ struct VerificPass : public Pass { } #else /* YOSYS_ENABLE_VERIFIC */ - void execute(std::vector, RTLIL::Design *) YS_OVERRIDE { + void execute(std::vector, RTLIL::Design *) override { log_cmd_error("This version of Yosys is built without Verific support.\n" "\n" "Use Symbiotic EDA Suite if you need Yosys+Verifc.\n" @@ -2596,7 +2596,7 @@ struct VerificPass : public Pass { struct ReadPass : public Pass { ReadPass() : Pass("read", "load HDL designs") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -2637,7 +2637,7 @@ struct ReadPass : public Pass { log("Verific support. The default is to use Verific if it is available.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { #ifdef YOSYS_ENABLE_VERIFIC static bool verific_available = !check_noverific_env(); diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 26abe49b5..2e9c9b2e2 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -67,7 +67,7 @@ static void add_package_types(dict &user_types, std struct VerilogFrontend : public Frontend { VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -232,7 +232,7 @@ struct VerilogFrontend : public Frontend { log("supported by the Yosys Verilog front-end.\n"); log("\n"); } - void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { bool flag_dump_ast1 = false; bool flag_dump_ast2 = false; @@ -503,7 +503,7 @@ struct VerilogFrontend : public Frontend { struct VerilogDefaults : public Pass { VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -524,7 +524,7 @@ struct VerilogDefaults : public Pass { log("not imply -clear.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design*) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design*) override { if (args.size() < 2) cmd_error(args, 1, "Missing argument."); @@ -561,7 +561,7 @@ struct VerilogDefaults : public Pass { struct VerilogDefines : public Pass { VerilogDefines() : Pass("verilog_defines", "define and undefine verilog defines") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -583,7 +583,7 @@ struct VerilogDefines : public Pass { log(" list currently defined preprocessor symbols\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { diff --git a/kernel/celledges.h b/kernel/celledges.h index 2cc297cb2..d105e4009 100644 --- a/kernel/celledges.h +++ b/kernel/celledges.h @@ -38,7 +38,7 @@ struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase dict> db; FwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { } - void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE { + void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override { SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]); SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]); db[from_sigbit].insert(to_sigbit); @@ -51,7 +51,7 @@ struct RevCellEdgesDatabase : AbstractCellEdgesDatabase dict> db; RevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { } - void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE { + void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override { SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]); SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]); db[to_sigbit].insert(from_sigbit); diff --git a/kernel/modtools.h b/kernel/modtools.h index fbc5482ee..9d6a50502 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -158,7 +158,7 @@ struct ModIndex : public RTLIL::Monitor #endif } - void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) YS_OVERRIDE + void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override { log_assert(module == cell->module); @@ -169,7 +169,7 @@ struct ModIndex : public RTLIL::Monitor port_add(cell, port, sig); } - void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) YS_OVERRIDE + void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) override { log_assert(module == mod); @@ -214,13 +214,13 @@ struct ModIndex : public RTLIL::Monitor } } - void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector&) YS_OVERRIDE + void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector&) override { log_assert(module == mod); auto_reload_module = true; } - void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) YS_OVERRIDE + void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) override { log_assert(module == mod); auto_reload_module = true; diff --git a/kernel/register.cc b/kernel/register.cc index 02974e534..34735a608 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -753,7 +753,7 @@ static struct CellHelpMessages { struct HelpPass : public Pass { HelpPass() : Pass("help", "display help messages") { } - void help() YS_OVERRIDE + void help() override { log("\n"); log(" help ................ list all commands\n"); @@ -822,7 +822,7 @@ struct HelpPass : public Pass { fclose(f); } - void execute(std::vector args, RTLIL::Design*) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design*) override { if (args.size() == 1) { log("\n"); @@ -926,7 +926,7 @@ struct HelpPass : public Pass { struct EchoPass : public Pass { EchoPass() : Pass("echo", "turning echoing back of commands on and off") { } - void help() YS_OVERRIDE + void help() override { log("\n"); log(" echo on\n"); @@ -939,7 +939,7 @@ struct EchoPass : public Pass { log("Do not print all commands to log before executing them. (default)\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design*) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design*) override { if (args.size() > 2) cmd_error(args, 2, "Unexpected argument."); @@ -964,7 +964,7 @@ struct MinisatSatSolver : public SatSolver { MinisatSatSolver() : SatSolver("minisat") { yosys_satsolver = this; } - ezSAT *create() YS_OVERRIDE { + ezSAT *create() override { return new ezMiniSAT(); } } MinisatSatSolver; diff --git a/kernel/register.h b/kernel/register.h index 7bbcd1727..5cd849082 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -97,9 +97,9 @@ struct Frontend : Pass std::string frontend_name; Frontend(std::string name, std::string short_help = "** document me **"); - void run_register() YS_OVERRIDE; - ~Frontend() YS_OVERRIDE; - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL; + void run_register() override; + ~Frontend() override; + void execute(std::vector args, RTLIL::Design *design) override final; virtual void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design *design) = 0; static std::vector next_args; @@ -113,9 +113,9 @@ struct Backend : Pass { std::string backend_name; Backend(std::string name, std::string short_help = "** document me **"); - void run_register() YS_OVERRIDE; - ~Backend() YS_OVERRIDE; - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL; + void run_register() override; + ~Backend() override; + void execute(std::vector args, RTLIL::Design *design) override final; virtual void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) = 0; void extra_args(std::ostream *&f, std::string &filename, std::vector args, size_t argidx, bool bin_output = false); diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 2ec3dca0c..7e9f320e0 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -713,7 +713,7 @@ extern Tcl_Interp *yosys_get_tcl_interp() struct TclPass : public Pass { TclPass() : Pass("tcl", "execute a TCL script file") { } - void help() YS_OVERRIDE { + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" tcl [args]\n"); @@ -730,7 +730,7 @@ struct TclPass : public Pass { log("the standard $argc and $argv variables.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *) YS_OVERRIDE { + void execute(std::vector args, RTLIL::Design *) override { if (args.size() < 2) log_cmd_error("Missing script file.\n"); @@ -1220,7 +1220,7 @@ void shell(RTLIL::Design *design) struct ShellPass : public Pass { ShellPass() : Pass("shell", "enter interactive command mode") { } - void help() YS_OVERRIDE { + void help() override { log("\n"); log(" shell\n"); log("\n"); @@ -1252,7 +1252,7 @@ struct ShellPass : public Pass { log("Press Ctrl-D or type 'exit' to leave the interactive shell.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { + void execute(std::vector args, RTLIL::Design *design) override { extra_args(args, 1, design, false); shell(design); } @@ -1261,7 +1261,7 @@ struct ShellPass : public Pass { #if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE) struct HistoryPass : public Pass { HistoryPass() : Pass("history", "show last interactive commands") { } - void help() YS_OVERRIDE { + void help() override { log("\n"); log(" history\n"); log("\n"); @@ -1270,7 +1270,7 @@ struct HistoryPass : public Pass { log("from executed scripts.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { + void execute(std::vector args, RTLIL::Design *design) override { extra_args(args, 1, design, false); #ifdef YOSYS_ENABLE_READLINE for(HIST_ENTRY **list = history_list(); *list != NULL; list++) @@ -1285,7 +1285,7 @@ struct HistoryPass : public Pass { struct ScriptCmdPass : public Pass { ScriptCmdPass() : Pass("script", "execute commands from file or wire") { } - void help() YS_OVERRIDE { + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" script [:]\n"); @@ -1308,7 +1308,7 @@ struct ScriptCmdPass : public Pass { log("'-module' mode can be exited by using the 'cd' command.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool scriptwire = false; diff --git a/kernel/yosys.h b/kernel/yosys.h index 4fca39228..4510ee56b 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -136,14 +136,6 @@ extern Tcl_Obj *Tcl_ObjSetVar2(Tcl_Interp *interp, Tcl_Obj *part1Ptr, Tcl_Obj *p #define YOSYS_NAMESPACE_PREFIX Yosys:: #define USING_YOSYS_NAMESPACE using namespace Yosys; -#if __cplusplus >= 201103L -# define YS_OVERRIDE override -# define YS_FINAL final -#else -# define YS_OVERRIDE -# define YS_FINAL -#endif - #if defined(__GNUC__) || defined(__clang__) # define YS_ATTRIBUTE(...) __attribute__((__VA_ARGS__)) # define YS_NORETURN diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc index 8123e63db..566d24b18 100644 --- a/manual/CHAPTER_Prog/stubnets.cc +++ b/manual/CHAPTER_Prog/stubnets.cc @@ -98,7 +98,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re // each pass contains a singleton object that is derived from Pass struct StubnetsPass : public Pass { StubnetsPass() : Pass("stubnets") { } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { // variables to mirror information from passed options bool report_bits = 0; diff --git a/manual/PRESENTATION_Prog/my_cmd.cc b/manual/PRESENTATION_Prog/my_cmd.cc index 5d9a7e13b..9cb4b8e38 100644 --- a/manual/PRESENTATION_Prog/my_cmd.cc +++ b/manual/PRESENTATION_Prog/my_cmd.cc @@ -6,7 +6,7 @@ PRIVATE_NAMESPACE_BEGIN struct MyPass : public Pass { MyPass() : Pass("my_cmd", "just a simple test") { } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log("Arguments to my_cmd:\n"); for (auto &arg : args) @@ -22,7 +22,7 @@ struct MyPass : public Pass { struct Test1Pass : public Pass { Test1Pass() : Pass("test1", "creating the absval module") { } - void execute(std::vector, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector, RTLIL::Design *design) override { if (design->has("\\absval") != 0) log_error("A module with the name absval already exists!\n"); @@ -49,7 +49,7 @@ struct Test1Pass : public Pass { struct Test2Pass : public Pass { Test2Pass() : Pass("test2", "demonstrating sigmap on test module") { } - void execute(std::vector, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector, RTLIL::Design *design) override { if (design->selection_stack.back().empty()) log_cmd_error("This command can't operator on an empty selection!\n"); diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 91f8c2add..a2f4a9100 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -116,7 +116,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n struct AddPass : public Pass { AddPass() : Pass("add", "add objects to the design") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -150,7 +150,7 @@ struct AddPass : public Pass { log("Add module[s] with the specified name[s].\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::string command; std::string arg_name; diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc index 50632201e..28d4012c4 100644 --- a/passes/cmds/autoname.cc +++ b/passes/cmds/autoname.cc @@ -92,7 +92,7 @@ int autoname_worker(Module *module) struct AutonamePass : public Pass { AutonamePass() : Pass("autoname", "automatically assign names to objects") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -102,7 +102,7 @@ struct AutonamePass : public Pass { log("with $-prefix).\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) diff --git a/passes/cmds/blackbox.cc b/passes/cmds/blackbox.cc index b8297cd77..08a635514 100644 --- a/passes/cmds/blackbox.cc +++ b/passes/cmds/blackbox.cc @@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN struct BlackboxPass : public Pass { BlackboxPass() : Pass("blackbox", "convert modules into blackbox modules") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -34,7 +34,7 @@ struct BlackboxPass : public Pass { log("module attribute).\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index 00aac596f..98d42aa83 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -26,7 +26,7 @@ PRIVATE_NAMESPACE_BEGIN struct BugpointPass : public Pass { BugpointPass() : Pass("bugpoint", "minimize testcases") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -313,7 +313,7 @@ struct BugpointPass : public Pass { return nullptr; } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { string yosys_cmd = "yosys", script, grep; bool fast = false, clean = false; diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index ba29e6f4b..a8b5362b3 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct CheckPass : public Pass { CheckPass() : Pass("check", "check for obvious problems in the design") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -61,7 +61,7 @@ struct CheckPass : public Pass { log(" Produce a runtime error if any problems are found in the current design.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { int counter = 0; bool noinit = false; diff --git a/passes/cmds/chformal.cc b/passes/cmds/chformal.cc index d6e7f2ccf..a1b3fbef7 100644 --- a/passes/cmds/chformal.cc +++ b/passes/cmds/chformal.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct ChformalPass : public Pass { ChformalPass() : Pass("chformal", "change formal constraints of the design") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -62,7 +62,7 @@ struct ChformalPass : public Pass { log(" change the roles of cells as indicated. these options can be combined\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool assert2assume = false; bool assume2assert = false; diff --git a/passes/cmds/chtype.cc b/passes/cmds/chtype.cc index 979aeadd4..b894f334c 100644 --- a/passes/cmds/chtype.cc +++ b/passes/cmds/chtype.cc @@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN struct ChtypePass : public Pass { ChtypePass() : Pass("chtype", "change type of cells in the design") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -40,7 +40,7 @@ struct ChtypePass : public Pass { log("\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { IdString set_type; dict map_types; diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 0b0868dfb..0cc6cbe52 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -43,7 +43,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & struct ConnectPass : public Pass { ConnectPass() : Pass("connect", "create or remove connections") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -75,7 +75,7 @@ struct ConnectPass : public Pass { log("This command does not operate on module with processes.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { RTLIL::Module *module = nullptr; for (auto mod : design->selected_modules()) { diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index 6ae7c9304..9235dda2b 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -143,7 +143,7 @@ struct ConnwrappersWorker struct ConnwrappersPass : public Pass { ConnwrappersPass() : Pass("connwrappers", "match width of input-output port pairs") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -165,7 +165,7 @@ struct ConnwrappersPass : public Pass { log("The options -signed, -unsigned, and -port can be specified multiple times.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { ConnwrappersWorker worker; diff --git a/passes/cmds/copy.cc b/passes/cmds/copy.cc index 99f1f69cf..c351065f3 100644 --- a/passes/cmds/copy.cc +++ b/passes/cmds/copy.cc @@ -26,7 +26,7 @@ PRIVATE_NAMESPACE_BEGIN struct CopyPass : public Pass { CopyPass() : Pass("copy", "copy modules in the design") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -36,7 +36,7 @@ struct CopyPass : public Pass { log("by this command.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { if (args.size() != 3) log_cmd_error("Invalid number of arguments!\n"); diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc index 89d27c9aa..0867e3b4f 100644 --- a/passes/cmds/cover.cc +++ b/passes/cmds/cover.cc @@ -35,7 +35,7 @@ PRIVATE_NAMESPACE_BEGIN struct CoverPass : public Pass { CoverPass() : Pass("cover", "print code coverage counters") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -83,7 +83,7 @@ struct CoverPass : public Pass { log("Coverage counters are only available in Yosys for Linux.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::vector out_files; std::vector patterns; diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index b124e3b0f..684fa37b0 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN struct DeletePass : public Pass { DeletePass() : Pass("delete", "delete objects in the design") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -40,7 +40,7 @@ struct DeletePass : public Pass { log("selected wires, thus 'deleting' module ports.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool flag_input = false; bool flag_output = false; diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 421defe0c..2d7ba1fef 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -28,7 +28,7 @@ std::vector pushed_designs; struct DesignPass : public Pass { DesignPass() : Pass("design", "save, restore and reset current design") { } - ~DesignPass() YS_OVERRIDE { + ~DesignPass() override { for (auto &it : saved_designs) delete it.second; saved_designs.clear(); @@ -36,7 +36,7 @@ struct DesignPass : public Pass { delete it; pushed_designs.clear(); } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -105,7 +105,7 @@ struct DesignPass : public Pass { log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool got_mode = false; bool reset_mode = false; diff --git a/passes/cmds/edgetypes.cc b/passes/cmds/edgetypes.cc index 58ed6457d..37c420400 100644 --- a/passes/cmds/edgetypes.cc +++ b/passes/cmds/edgetypes.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct EdgetypePass : public Pass { EdgetypePass() : Pass("edgetypes", "list all types of edges in selection") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -35,7 +35,7 @@ struct EdgetypePass : public Pass { log("is a 4-tuple of source and sink cell type and port name.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { diff --git a/passes/cmds/exec.cc b/passes/cmds/exec.cc index 7eeefe705..951fa53fc 100644 --- a/passes/cmds/exec.cc +++ b/passes/cmds/exec.cc @@ -38,7 +38,7 @@ PRIVATE_NAMESPACE_BEGIN struct ExecPass : public Pass { ExecPass() : Pass("exec", "execute commands in the operating system shell") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -71,7 +71,7 @@ struct ExecPass : public Pass { log("\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::string cmd = ""; char buf[1024] = {}; diff --git a/passes/cmds/logcmd.cc b/passes/cmds/logcmd.cc index 522e1089d..12c43ecec 100644 --- a/passes/cmds/logcmd.cc +++ b/passes/cmds/logcmd.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct LogPass : public Pass { LogPass() : Pass("log", "print text and log files") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -52,7 +52,7 @@ struct LogPass : public Pass { log(" do not append a newline\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design*) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design*) override { size_t argidx; bool to_stdout = false; diff --git a/passes/cmds/logger.cc b/passes/cmds/logger.cc index c9532eced..6a9ed6036 100644 --- a/passes/cmds/logger.cc +++ b/passes/cmds/logger.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct LoggerPass : public Pass { LoggerPass() : Pass("logger", "set logger properties") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -66,7 +66,7 @@ struct LoggerPass : public Pass { log("\n"); } - void execute(std::vector args, RTLIL::Design * design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design * design) override { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) diff --git a/passes/cmds/ltp.cc b/passes/cmds/ltp.cc index 05701710b..39ec432c2 100644 --- a/passes/cmds/ltp.cc +++ b/passes/cmds/ltp.cc @@ -141,7 +141,7 @@ struct LtpWorker struct LtpPass : public Pass { LtpPass() : Pass("ltp", "print longest topological path") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -154,7 +154,7 @@ struct LtpPass : public Pass { log(" automatically exclude FF cell types\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool noff = false; diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index 4c16b56c4..3ed19497d 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -99,7 +99,7 @@ void load_plugin(std::string, std::vector) struct PluginPass : public Pass { PluginPass() : Pass("plugin", "load and list loaded plugins") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -117,7 +117,7 @@ struct PluginPass : public Pass { log(" List loaded plugins\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::string plugin_filename; std::vector plugin_aliases; diff --git a/passes/cmds/portlist.cc b/passes/cmds/portlist.cc index 38c4a8597..97f4bfd99 100644 --- a/passes/cmds/portlist.cc +++ b/passes/cmds/portlist.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct PortlistPass : public Pass { PortlistPass() : Pass("portlist", "list (top-level) ports") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -39,7 +39,7 @@ struct PortlistPass : public Pass { log(" print verilog blackbox module definitions instead of port lists\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool m_mode = false; diff --git a/passes/cmds/printattrs.cc b/passes/cmds/printattrs.cc index 80dbfa259..7973ac262 100644 --- a/passes/cmds/printattrs.cc +++ b/passes/cmds/printattrs.cc @@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN struct PrintAttrsPass : public Pass { PrintAttrsPass() : Pass("printattrs", "print attributes of selected objects") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -48,7 +48,7 @@ struct PrintAttrsPass : public Pass { log_assert(x.flags == RTLIL::CONST_FLAG_STRING || x.flags == RTLIL::CONST_FLAG_NONE); //intended to fail } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { size_t argidx = 1; extra_args(args, argidx, design); diff --git a/passes/cmds/qwp.cc b/passes/cmds/qwp.cc index b178ef951..cf0f6d0de 100644 --- a/passes/cmds/qwp.cc +++ b/passes/cmds/qwp.cc @@ -778,7 +778,7 @@ struct QwpWorker struct QwpPass : public Pass { QwpPass() : Pass("qwp", "quadratic wirelength placer") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -808,7 +808,7 @@ struct QwpPass : public Pass { log("dense matrix operations. It is only a toy-placer for small circuits.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { QwpConfig config; xorshift32_state = 123456789; diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 7d6d84d42..6326b4b15 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -104,7 +104,7 @@ static IdString derive_name_from_cell_output_wire(const RTLIL::Cell *cell) struct RenamePass : public Pass { RenamePass() : Pass("rename", "rename object in the design") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -152,7 +152,7 @@ struct RenamePass : public Pass { log("Rename top module.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::string pattern_prefix = "_", pattern_suffix = "_"; bool flag_src = false; diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index a5ef95f02..a70dd3086 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct ScatterPass : public Pass { ScatterPass() : Pass("scatter", "add additional intermediate nets") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -41,7 +41,7 @@ struct ScatterPass : public Pass { log("Use the opt_clean command to get rid of the additional nets.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { CellTypes ct(design); extra_args(args, 1, design); diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index ad0554bae..8e7f3f990 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -218,7 +218,7 @@ struct SccWorker struct SccPass : public Pass { SccPass() : Pass("scc", "detect strongly connected components (logic loops)") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -255,7 +255,7 @@ struct SccPass : public Pass { log(" that are part of a found logic loop\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::map setAttr; bool allCellTypes = false; diff --git a/passes/cmds/scratchpad.cc b/passes/cmds/scratchpad.cc index 34ec0863a..9369f5312 100644 --- a/passes/cmds/scratchpad.cc +++ b/passes/cmds/scratchpad.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct ScratchpadPass : public Pass { ScratchpadPass() : Pass("scratchpad", "get/set values in the scratchpad") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -63,7 +63,7 @@ struct ScratchpadPass : public Pass { log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 13ee030a5..b4f3994a2 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -1021,7 +1021,7 @@ PRIVATE_NAMESPACE_BEGIN struct SelectPass : public Pass { SelectPass() : Pass("select", "modify and view the list of selected objects") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1250,7 +1250,7 @@ struct SelectPass : public Pass { log(" select */t:SWITCH %%x:+[GATE] */t:SWITCH %%d\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool add_mode = false; bool del_mode = false; @@ -1587,7 +1587,7 @@ struct SelectPass : public Pass { struct CdPass : public Pass { CdPass() : Pass("cd", "a shortcut for 'select -module '") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1613,7 +1613,7 @@ struct CdPass : public Pass { log("This is just a shortcut for 'select -clear'.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { if (args.size() != 1 && args.size() != 2) log_cmd_error("Invalid number of arguments.\n"); @@ -1693,7 +1693,7 @@ static void log_matches(const char *title, Module *module, const T &list) struct LsPass : public Pass { LsPass() : Pass("ls", "list modules or objects in modules") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1704,7 +1704,7 @@ struct LsPass : public Pass { log("When an active module is selected, this prints a list of objects in the module.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { size_t argidx = 1; extra_args(args, argidx, design); diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc index 515f5a4ef..3a94209d4 100644 --- a/passes/cmds/setattr.cc +++ b/passes/cmds/setattr.cc @@ -56,7 +56,7 @@ static void do_setunset(dict &attrs, const std::v struct SetattrPass : public Pass { SetattrPass() : Pass("setattr", "set/unset attributes on objects") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -69,7 +69,7 @@ struct SetattrPass : public Pass { log("instead of objects within modules.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::vector setunset_list; bool flag_mod = false; @@ -128,7 +128,7 @@ struct SetattrPass : public Pass { struct WbflipPass : public Pass { WbflipPass() : Pass("wbflip", "flip the whitebox attribute") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -138,7 +138,7 @@ struct WbflipPass : public Pass { log("vice-versa. Blackbox cells are not effected by this command.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -167,7 +167,7 @@ struct WbflipPass : public Pass { struct SetparamPass : public Pass { SetparamPass() : Pass("setparam", "set/unset parameters on objects") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -179,7 +179,7 @@ struct SetparamPass : public Pass { log("The -type option can be used to change the cell type of the selected cells.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { vector setunset_list; string new_cell_type; @@ -219,7 +219,7 @@ struct SetparamPass : public Pass { struct ChparamPass : public Pass { ChparamPass() : Pass("chparam", "re-evaluate modules with new parameters") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -234,7 +234,7 @@ struct ChparamPass : public Pass { log("List the available parameters of the selected modules.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::vector setunset_list; dict new_parameters; diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 8d973869e..cf8d76619 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -107,7 +107,7 @@ struct SetundefWorker struct SetundefPass : public Pass { SetundefPass() : Pass("setundef", "replace undef values with defined constants") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -147,7 +147,7 @@ struct SetundefPass : public Pass { log(" replace undef in cell parameters\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { int got_value = 0; bool undriven_mode = false; diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index fa922454a..cbed08a3f 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -587,7 +587,7 @@ struct ShowWorker struct ShowPass : public Pass { ShowPass() : Pass("show", "generate schematics using graphviz") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -674,7 +674,7 @@ struct ShowPass : public Pass { log("the 'show' command is executed.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Generating Graphviz representation of design.\n"); log_push(); diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index ea9e06979..20627d601 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -246,7 +246,7 @@ struct SpliceWorker struct SplicePass : public Pass { SplicePass() : Pass("splice", "create explicit splicing cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -287,7 +287,7 @@ struct SplicePass : public Pass { log("by selected wires are rewired.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool sel_by_cell = false; bool sel_by_wire = false; diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 303f084d2..fff8a0d3e 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -95,7 +95,7 @@ struct SplitnetsWorker struct SplitnetsPass : public Pass { SplitnetsPass() : Pass("splitnets", "split up multi-bit nets") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -117,7 +117,7 @@ struct SplitnetsPass : public Pass { log(" and split nets so that no driver drives only part of a net.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool flag_ports = false; bool flag_driver = false; diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 30436d829..6f2c2243e 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -282,7 +282,7 @@ void read_liberty_cellarea(dict &cell_area, string liberty_fil struct StatPass : public Pass { StatPass() : Pass("stat", "print some statistics") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -308,7 +308,7 @@ struct StatPass : public Pass { log(" e.g. $add_8 for an 8 bit wide $add cell.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Printing statistics.\n"); diff --git a/passes/cmds/tee.cc b/passes/cmds/tee.cc index 1a44bdaec..60689fc82 100644 --- a/passes/cmds/tee.cc +++ b/passes/cmds/tee.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct TeePass : public Pass { TeePass() : Pass("tee", "redirect command output to file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -49,7 +49,7 @@ struct TeePass : public Pass { log(" Add/subtract INT from the -v setting for this command.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::vector backup_log_files, files_to_close; std::vector backup_log_streams; diff --git a/passes/cmds/torder.cc b/passes/cmds/torder.cc index 5748ff7f0..30e76081e 100644 --- a/passes/cmds/torder.cc +++ b/passes/cmds/torder.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct TorderPass : public Pass { TorderPass() : Pass("torder", "print cells in topological order") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -43,7 +43,7 @@ struct TorderPass : public Pass { log(" are not used in topological sorting. this option deactivates that.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool noautostop = false; dict> stop_db; diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc index 8446e27b3..10742c370 100644 --- a/passes/cmds/trace.cc +++ b/passes/cmds/trace.cc @@ -25,34 +25,34 @@ PRIVATE_NAMESPACE_BEGIN struct TraceMonitor : public RTLIL::Monitor { - void notify_module_add(RTLIL::Module *module) YS_OVERRIDE + void notify_module_add(RTLIL::Module *module) override { log("#TRACE# Module add: %s\n", log_id(module)); } - void notify_module_del(RTLIL::Module *module) YS_OVERRIDE + void notify_module_del(RTLIL::Module *module) override { log("#TRACE# Module delete: %s\n", log_id(module)); } - void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) YS_OVERRIDE + void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override { log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig)); } - void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) YS_OVERRIDE + void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) override { log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second)); } - void notify_connect(RTLIL::Module *module, const std::vector &sigsig_vec) YS_OVERRIDE + void notify_connect(RTLIL::Module *module, const std::vector &sigsig_vec) override { log("#TRACE# New connections in module %s:\n", log_id(module)); for (auto &sigsig : sigsig_vec) log("## %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second)); } - void notify_blackout(RTLIL::Module *module) YS_OVERRIDE + void notify_blackout(RTLIL::Module *module) override { log("#TRACE# Blackout in module %s:\n", log_id(module)); } @@ -60,7 +60,7 @@ struct TraceMonitor : public RTLIL::Monitor struct TracePass : public Pass { TracePass() : Pass("trace", "redirect command output to file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -70,7 +70,7 @@ struct TracePass : public Pass { log("the design in real time.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -96,7 +96,7 @@ struct TracePass : public Pass { struct DebugPass : public Pass { DebugPass() : Pass("debug", "run command with debug log messages enabled") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -105,7 +105,7 @@ struct DebugPass : public Pass { log("Execute the specified command with debug log messages enabled\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) diff --git a/passes/cmds/write_file.cc b/passes/cmds/write_file.cc index 64a762d7c..3d898a5ef 100644 --- a/passes/cmds/write_file.cc +++ b/passes/cmds/write_file.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct WriteFileFrontend : public Frontend { WriteFileFrontend() : Frontend("=write_file", "write a text to a file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -44,7 +44,7 @@ struct WriteFileFrontend : public Frontend { log(" EOT\n"); log("\n"); } - void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design*) YS_OVERRIDE + void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design*) override { bool append_mode = false; std::string output_filename; diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc index cdc74b0b2..2abbb59bb 100644 --- a/passes/equiv/equiv_add.cc +++ b/passes/equiv/equiv_add.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct EquivAddPass : public Pass { EquivAddPass() : Pass("equiv_add", "add a $equiv cell") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -39,7 +39,7 @@ struct EquivAddPass : public Pass { log("This command adds $equiv cells for the ports of the specified cells.\n"); log("\n"); } - void execute(std::vector args, Design *design) YS_OVERRIDE + void execute(std::vector args, Design *design) override { bool try_mode = false; diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc index ec651193e..596c938fc 100644 --- a/passes/equiv/equiv_induct.cc +++ b/passes/equiv/equiv_induct.cc @@ -162,7 +162,7 @@ struct EquivInductWorker struct EquivInductPass : public Pass { EquivInductPass() : Pass("equiv_induct", "proving $equiv cells using temporal induction") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -192,7 +192,7 @@ struct EquivInductPass : public Pass { log("after reset.\n"); log("\n"); } - void execute(std::vector args, Design *design) YS_OVERRIDE + void execute(std::vector args, Design *design) override { int success_counter = 0; bool model_undef = false; diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index 50572ae5c..51b4ad0f1 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -466,7 +466,7 @@ struct EquivMakeWorker struct EquivMakePass : public Pass { EquivMakePass() : Pass("equiv_make", "prepare a circuit for equivalence checking") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -491,7 +491,7 @@ struct EquivMakePass : public Pass { log("checking problem. Use 'miter -equiv' if you want to create a miter circuit.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { EquivMakeWorker worker; worker.ct.setup(design); diff --git a/passes/equiv/equiv_mark.cc b/passes/equiv/equiv_mark.cc index 737de25d9..a722b5ed6 100644 --- a/passes/equiv/equiv_mark.cc +++ b/passes/equiv/equiv_mark.cc @@ -204,7 +204,7 @@ struct EquivMarkWorker struct EquivMarkPass : public Pass { EquivMarkPass() : Pass("equiv_mark", "mark equivalence checking regions") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -216,7 +216,7 @@ struct EquivMarkPass : public Pass { log("wires and cells.\n"); log("\n"); } - void execute(std::vector args, Design *design) YS_OVERRIDE + void execute(std::vector args, Design *design) override { log_header(design, "Executing EQUIV_MARK pass.\n"); diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc index 085970189..e028f806a 100644 --- a/passes/equiv/equiv_miter.cc +++ b/passes/equiv/equiv_miter.cc @@ -261,7 +261,7 @@ struct EquivMiterWorker struct EquivMiterPass : public Pass { EquivMiterPass() : Pass("equiv_miter", "extract miter from equiv circuit") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -282,7 +282,7 @@ struct EquivMiterPass : public Pass { log(" Create compare logic that handles undefs correctly\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { EquivMiterWorker worker; worker.ct.setup(design); diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc index 7c6c2e685..4d0400448 100644 --- a/passes/equiv/equiv_opt.cc +++ b/passes/equiv/equiv_opt.cc @@ -26,7 +26,7 @@ struct EquivOptPass:public ScriptPass { EquivOptPass() : ScriptPass("equiv_opt", "prove equivalence for optimized circuit") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -68,7 +68,7 @@ struct EquivOptPass:public ScriptPass std::string command, techmap_opts, make_opts; bool assert, undef, multiclock, async2sync; - void clear_flags() YS_OVERRIDE + void clear_flags() override { command = ""; techmap_opts = ""; @@ -79,7 +79,7 @@ struct EquivOptPass:public ScriptPass async2sync = false; } - void execute(std::vector < std::string > args, RTLIL::Design * design) YS_OVERRIDE + void execute(std::vector < std::string > args, RTLIL::Design * design) override { string run_from, run_to; clear_flags(); @@ -148,7 +148,7 @@ struct EquivOptPass:public ScriptPass log_pop(); } - void script() YS_OVERRIDE + void script() override { if (check_label("run_pass")) { run("hierarchy -auto-top"); diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc index 688c20f43..d15c8d183 100644 --- a/passes/equiv/equiv_purge.cc +++ b/passes/equiv/equiv_purge.cc @@ -176,7 +176,7 @@ struct EquivPurgeWorker struct EquivPurgePass : public Pass { EquivPurgePass() : Pass("equiv_purge", "purge equivalence checking module") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -187,7 +187,7 @@ struct EquivPurgePass : public Pass { log("ports as needed.\n"); log("\n"); } - void execute(std::vector args, Design *design) YS_OVERRIDE + void execute(std::vector args, Design *design) override { log_header(design, "Executing EQUIV_PURGE pass.\n"); diff --git a/passes/equiv/equiv_remove.cc b/passes/equiv/equiv_remove.cc index 6daa112b5..89442308b 100644 --- a/passes/equiv/equiv_remove.cc +++ b/passes/equiv/equiv_remove.cc @@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN struct EquivRemovePass : public Pass { EquivRemovePass() : Pass("equiv_remove", "remove $equiv cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -40,7 +40,7 @@ struct EquivRemovePass : public Pass { log(" keep gate circuit\n"); log("\n"); } - void execute(std::vector args, Design *design) YS_OVERRIDE + void execute(std::vector args, Design *design) override { bool mode_gold = false; bool mode_gate = false; diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc index 4d2839f4d..408c5a793 100644 --- a/passes/equiv/equiv_simple.cc +++ b/passes/equiv/equiv_simple.cc @@ -273,7 +273,7 @@ struct EquivSimpleWorker struct EquivSimplePass : public Pass { EquivSimplePass() : Pass("equiv_simple", "try proving simple $equiv instances") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -298,7 +298,7 @@ struct EquivSimplePass : public Pass { log(" the max. number of time steps to be considered (default = 1)\n"); log("\n"); } - void execute(std::vector args, Design *design) YS_OVERRIDE + void execute(std::vector args, Design *design) override { bool verbose = false, short_cones = false, model_undef = false, nogroup = false; int success_counter = 0; diff --git a/passes/equiv/equiv_status.cc b/passes/equiv/equiv_status.cc index 258e2e45b..2db44ea90 100644 --- a/passes/equiv/equiv_status.cc +++ b/passes/equiv/equiv_status.cc @@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN struct EquivStatusPass : public Pass { EquivStatusPass() : Pass("equiv_status", "print status of equivalent checking module") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -36,7 +36,7 @@ struct EquivStatusPass : public Pass { log(" produce an error if any unproven $equiv cell is found\n"); log("\n"); } - void execute(std::vector args, Design *design) YS_OVERRIDE + void execute(std::vector args, Design *design) override { bool assert_mode = false; int unproven_count = 0; diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc index 1b7bf96a8..9784225db 100644 --- a/passes/equiv/equiv_struct.cc +++ b/passes/equiv/equiv_struct.cc @@ -283,7 +283,7 @@ struct EquivStructWorker struct EquivStructPass : public Pass { EquivStructPass() : Pass("equiv_struct", "structural equivalence checking") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -314,7 +314,7 @@ struct EquivStructPass : public Pass { log(" maximum number of iterations to run before aborting\n"); log("\n"); } - void execute(std::vector args, Design *design) YS_OVERRIDE + void execute(std::vector args, Design *design) override { pool fwonly_cells({ ID($equiv) }); bool mode_icells = false; diff --git a/passes/fsm/fsm.cc b/passes/fsm/fsm.cc index c5cb338ab..21d352407 100644 --- a/passes/fsm/fsm.cc +++ b/passes/fsm/fsm.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct FsmPass : public Pass { FsmPass() : Pass("fsm", "extract and optimize finite state machines") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -68,7 +68,7 @@ struct FsmPass : public Pass { log(" passed through to fsm_recode pass\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool flag_nomap = false; bool flag_norecode = false; diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 30e9e4dad..97c575ba7 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -257,7 +257,7 @@ static void detect_fsm(RTLIL::Wire *wire) struct FsmDetectPass : public Pass { FsmDetectPass() : Pass("fsm_detect", "finding FSMs in design") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -273,7 +273,7 @@ struct FsmDetectPass : public Pass { log("'fsm_encoding' attribute to \"none\".\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing FSM_DETECT pass (finding FSMs in design).\n"); extra_args(args, 1, design); diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index ade6c17f5..d6b492af5 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -265,7 +265,7 @@ struct FsmExpand struct FsmExpandPass : public Pass { FsmExpandPass() : Pass("fsm_expand", "expand FSM cells by merging logic into it") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -279,7 +279,7 @@ struct FsmExpandPass : public Pass { log("word-wide cells. Call with -full to consider all cells for merging.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool full_mode = false; diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index c02a54ea2..be6702d7e 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -120,7 +120,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st */ struct FsmExportPass : public Pass { FsmExportPass() : Pass("fsm_export", "exporting FSMs to KISS2 files") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -143,7 +143,7 @@ struct FsmExportPass : public Pass { log(" use binary state encoding as state names instead of s0, s1, ...\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { dict::iterator attr_it; std::string arg; diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 6f99886f0..082973153 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -401,7 +401,7 @@ static void extract_fsm(RTLIL::Wire *wire) struct FsmExtractPass : public Pass { FsmExtractPass() : Pass("fsm_extract", "extracting FSMs in design") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -417,7 +417,7 @@ struct FsmExtractPass : public Pass { log("'opt_clean' pass to eliminate this signal.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n"); extra_args(args, 1, design); diff --git a/passes/fsm/fsm_info.cc b/passes/fsm/fsm_info.cc index 90250f9b7..da0982bb9 100644 --- a/passes/fsm/fsm_info.cc +++ b/passes/fsm/fsm_info.cc @@ -30,7 +30,7 @@ PRIVATE_NAMESPACE_BEGIN struct FsmInfoPass : public Pass { FsmInfoPass() : Pass("fsm_info", "print information on finite state machines") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -41,7 +41,7 @@ struct FsmInfoPass : public Pass { log("pass so that this information is included in the synthesis log file.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n"); extra_args(args, 1, design); diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 1765df092..a30d407f0 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -322,7 +322,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module) struct FsmMapPass : public Pass { FsmMapPass() : Pass("fsm_map", "mapping FSMs to basic logic") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -331,7 +331,7 @@ struct FsmMapPass : public Pass { log("This pass translates FSM cells to flip-flops and logic.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n"); extra_args(args, 1, design); diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 89e8132d4..5fc1fb3bb 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -324,7 +324,7 @@ PRIVATE_NAMESPACE_BEGIN struct FsmOptPass : public Pass { FsmOptPass() : Pass("fsm_opt", "optimize finite state machines") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -335,7 +335,7 @@ struct FsmOptPass : public Pass { log("combination with the 'opt_clean' pass (see also 'help fsm').\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n"); extra_args(args, 1, design); diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index 7edb923b9..d4a704270 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -126,7 +126,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs struct FsmRecodePass : public Pass { FsmRecodePass() : Pass("fsm_recode", "recoding finite state machines") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -151,7 +151,7 @@ struct FsmRecodePass : public Pass { log(" .map \n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { FILE *fm_set_fsm_file = NULL; FILE *encfile = NULL; diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index b4eb0f1dd..a2a428d15 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -558,7 +558,7 @@ RTLIL::Wire *find_implicit_port_wire(Module *module, Cell *cell, const std::stri struct HierarchyPass : public Pass { HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -639,7 +639,7 @@ struct HierarchyPass : public Pass { log("in the current design.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n"); diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 2db7cf26b..b2826cbff 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -319,7 +319,7 @@ struct SubmodWorker struct SubmodPass : public Pass { SubmodPass() : Pass("submod", "moving part of a module to a new submodule") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -351,7 +351,7 @@ struct SubmodPass : public Pass { log(" original module with original public names.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing SUBMOD pass (moving cells to submodules as requested).\n"); log_push(); diff --git a/passes/hierarchy/uniquify.cc b/passes/hierarchy/uniquify.cc index 5dbd15a7e..3f9443a63 100644 --- a/passes/hierarchy/uniquify.cc +++ b/passes/hierarchy/uniquify.cc @@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN struct UniquifyPass : public Pass { UniquifyPass() : Pass("uniquify", "create unique copies of modules") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -41,7 +41,7 @@ struct UniquifyPass : public Pass { log("attribute set (the 'top' module is unique implicitly).\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing UNIQUIFY pass (creating unique copies of modules).\n"); diff --git a/passes/memory/memory.cc b/passes/memory/memory.cc index cee63bdd8..282517992 100644 --- a/passes/memory/memory.cc +++ b/passes/memory/memory.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct MemoryPass : public Pass { MemoryPass() : Pass("memory", "translate memories to basic cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -49,7 +49,7 @@ struct MemoryPass : public Pass { log("or multiport memory blocks if called with the -nomap option.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool flag_nomap = false; bool flag_nordff = false; diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 0898ec288..3cb0728b7 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -1265,7 +1265,7 @@ void handle_cell(Cell *cell, const rules_t &rules) struct MemoryBramPass : public Pass { MemoryBramPass() : Pass("memory_bram", "map memories to block rams") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1367,7 +1367,7 @@ struct MemoryBramPass : public Pass { log("the data bits to accommodate the enable pattern of port A.\n"); log("\n"); } - void execute(vector args, Design *design) YS_OVERRIDE + void execute(vector args, Design *design) override { rules_t rules; diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index ef8b07811..7e82f47dc 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -245,7 +245,7 @@ static void handle_module(Design *design, Module *module) struct MemoryCollectPass : public Pass { MemoryCollectPass() : Pass("memory_collect", "creating multi-port memory cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -255,7 +255,7 @@ struct MemoryCollectPass : public Pass { log("memory cells.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing MEMORY_COLLECT pass (generating $mem cells).\n"); extra_args(args, 1, design); for (auto module : design->selected_modules()) diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 726a5c1ff..947cf7b35 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -291,7 +291,7 @@ struct MemoryDffWorker struct MemoryDffPass : public Pass { MemoryDffPass() : Pass("memory_dff", "merge input/output DFFs into memories") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -305,7 +305,7 @@ struct MemoryDffPass : public Pass { log(" do not merge registers on read ports\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool flag_wr_only = false; diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 9d455f55b..80dd3957d 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -403,7 +403,7 @@ struct MemoryMapWorker struct MemoryMapPass : public Pass { MemoryMapPass() : Pass("memory_map", "translate multiport memories to basic cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -425,7 +425,7 @@ struct MemoryMapPass : public Pass { log(" for -attr, ignore case of .\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool attr_icase = false; dict> attributes; diff --git a/passes/memory/memory_memx.cc b/passes/memory/memory_memx.cc index 5d5f61c7d..02e00cf30 100644 --- a/passes/memory/memory_memx.cc +++ b/passes/memory/memory_memx.cc @@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN struct MemoryMemxPass : public Pass { MemoryMemxPass() : Pass("memory_memx", "emulate vlog sim behavior for mem ports") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -38,7 +38,7 @@ struct MemoryMemxPass : public Pass { log("behavior for out-of-bounds memory reads and writes.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing MEMORY_MEMX pass (converting $mem cells to logic and flip-flops).\n"); extra_args(args, 1, design); diff --git a/passes/memory/memory_nordff.cc b/passes/memory/memory_nordff.cc index 487785397..07bbd9fe8 100644 --- a/passes/memory/memory_nordff.cc +++ b/passes/memory/memory_nordff.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct MemoryNordffPass : public Pass { MemoryNordffPass() : Pass("memory_nordff", "extract read port FFs from memories") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -35,7 +35,7 @@ struct MemoryNordffPass : public Pass { log("similar to what one would get from calling memory_dff with -nordff.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing MEMORY_NORDFF pass (extracting $dff cells from $mem).\n"); diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index e11958bd6..7315aeae1 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -734,7 +734,7 @@ struct MemoryShareWorker struct MemorySharePass : public Pass { MemorySharePass() : Pass("memory_share", "consolidate memory ports") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -760,7 +760,7 @@ struct MemorySharePass : public Pass { log("optimizations) such as \"share\" and \"opt_merge\".\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n"); extra_args(args, 1, design); MemoryShareWorker msw(design); diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 8d284edcd..d04d4ba7a 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -127,7 +127,7 @@ void handle_module(RTLIL::Design *design, RTLIL::Module *module) struct MemoryUnpackPass : public Pass { MemoryUnpackPass() : Pass("memory_unpack", "unpack multi-port memory cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -137,7 +137,7 @@ struct MemoryUnpackPass : public Pass { log("$memwr cells. It is the counterpart to the memory_collect pass.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n"); extra_args(args, 1, design); for (auto module : design->selected_modules()) diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc index 9df49ab3c..aa5f82437 100644 --- a/passes/opt/muxpack.cc +++ b/passes/opt/muxpack.cc @@ -326,7 +326,7 @@ struct MuxpackWorker struct MuxpackPass : public Pass { MuxpackPass() : Pass("muxpack", "$mux/$pmux cascades to $pmux") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -341,7 +341,7 @@ struct MuxpackPass : public Pass { log("certain that their select inputs are mutually exclusive.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing MUXPACK pass ($mux cell cascades to $pmux).\n"); diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc index b852e6ae8..8be94e345 100644 --- a/passes/opt/opt.cc +++ b/passes/opt/opt.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct OptPass : public Pass { OptPass() : Pass("opt", "perform simple optimizations") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -64,7 +64,7 @@ struct OptPass : public Pass { log("\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::string opt_clean_args; std::string opt_expr_args; diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index f7de02164..44de60b48 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -526,7 +526,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool struct OptCleanPass : public Pass { OptCleanPass() : Pass("opt_clean", "remove unused cells and wires") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -543,7 +543,7 @@ struct OptCleanPass : public Pass { log(" also remove internal nets if they have a public name\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool purge_mode = false; @@ -592,7 +592,7 @@ struct OptCleanPass : public Pass { struct CleanPass : public Pass { CleanPass() : Pass("clean", "remove unused cells and wires") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -607,7 +607,7 @@ struct CleanPass : public Pass { log("in -purge mode between the commands.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool purge_mode = false; diff --git a/passes/opt/opt_demorgan.cc b/passes/opt/opt_demorgan.cc index 4bc82815b..f0fa86f42 100644 --- a/passes/opt/opt_demorgan.cc +++ b/passes/opt/opt_demorgan.cc @@ -169,7 +169,7 @@ void demorgan_worker( struct OptDemorganPass : public Pass { OptDemorganPass() : Pass("opt_demorgan", "Optimize reductions with DeMorgan equivalents") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -179,7 +179,7 @@ struct OptDemorganPass : public Pass { log("overall gate count of the circuit\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing OPT_DEMORGAN pass (push inverters through $reduce_* cells).\n"); diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index e5b8bda95..c16f22b38 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -2009,7 +2009,7 @@ skip_alu_split: struct OptExprPass : public Pass { OptExprPass() : Pass("opt_expr", "perform const folding and simple expression rewriting") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -2043,7 +2043,7 @@ struct OptExprPass : public Pass { log(" replaced by 'a'. the -keepdc option disables all such optimizations.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool mux_undef = false; bool mux_bool = false; diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 12927d052..07a91af8a 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -520,7 +520,7 @@ static void split(std::vector &tokens, const std::string &text, cha struct OptLutPass : public Pass { OptLutPass() : Pass("opt_lut", "optimize LUT cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -538,7 +538,7 @@ struct OptLutPass : public Pass { log(" only perform the first N combines, then stop. useful for debugging.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing OPT_LUT pass (optimize LUTs).\n"); diff --git a/passes/opt/opt_lut_ins.cc b/passes/opt/opt_lut_ins.cc index 1d32e84bb..bb40e1e55 100644 --- a/passes/opt/opt_lut_ins.cc +++ b/passes/opt/opt_lut_ins.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct OptLutInsPass : public Pass { OptLutInsPass() : Pass("opt_lut_ins", "discard unused LUT inputs") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -42,7 +42,7 @@ struct OptLutInsPass : public Pass { log(" to the given technology. Valid values are: xilinx, ecp5, gowin.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing OPT_LUT_INS pass (discard unused LUT inputs).\n"); string techname; diff --git a/passes/opt/opt_mem.cc b/passes/opt/opt_mem.cc index ff9c06453..24df1356b 100644 --- a/passes/opt/opt_mem.cc +++ b/passes/opt/opt_mem.cc @@ -97,7 +97,7 @@ struct OptMemWorker struct OptMemPass : public Pass { OptMemPass() : Pass("opt_mem", "optimize memories") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -106,7 +106,7 @@ struct OptMemPass : public Pass { log("This pass performs various optimizations on memories in the design.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing OPT_MEM pass (optimize memories).\n"); diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index d845926fc..a95aa74c1 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -326,7 +326,7 @@ struct OptMergeWorker struct OptMergePass : public Pass { OptMergePass() : Pass("opt_merge", "consolidate identical cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -342,7 +342,7 @@ struct OptMergePass : public Pass { log(" Operate on all cell types, not just built-in types.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing OPT_MERGE pass (detect identical cells).\n"); diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index d076addae..67b283e11 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -473,7 +473,7 @@ struct OptMuxtreeWorker struct OptMuxtreePass : public Pass { OptMuxtreePass() : Pass("opt_muxtree", "eliminate dead trees in multiplexer trees") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -486,7 +486,7 @@ struct OptMuxtreePass : public Pass { log("This pass only operates on completely selected modules without processes.\n"); log("\n"); } - void execute(vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(vector args, RTLIL::Design *design) override { log_header(design, "Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n"); extra_args(args, 1, design); diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index f640f50a0..28de9ceb6 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -332,7 +332,7 @@ struct OptReduceWorker struct OptReducePass : public Pass { OptReducePass() : Pass("opt_reduce", "simplify large MUXes and AND/OR gates") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -353,7 +353,7 @@ struct OptReducePass : public Pass { log(" alias for -fine\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool do_fine = false; diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 81326a417..8f7628a4a 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -540,7 +540,7 @@ delete_dff: struct OptRmdffPass : public Pass { OptRmdffPass() : Pass("opt_rmdff", "remove DFFs with constant inputs") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -554,7 +554,7 @@ struct OptRmdffPass : public Pass { log(" non-constant inputs) that can also be replaced with a constant driver\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { int total_count = 0, total_initdrv = 0; log_header(design, "Executing OPT_RMDFF pass (remove dff with constant values).\n"); diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index cbace7bac..db21cef28 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -473,7 +473,7 @@ dict find_valid_op_mux_conns(RTLIL::Module *module, d struct OptSharePass : public Pass { OptSharePass() : Pass("opt_share", "merge mutually exclusive cells of the same type that share an input signal") {} - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -488,7 +488,7 @@ struct OptSharePass : public Pass { log("multiplexing its output to multiplexing the non-shared input signals.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing OPT_SHARE pass.\n"); diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc index 11b80b6b3..9a00f84b9 100644 --- a/passes/opt/pmux2shiftx.cc +++ b/passes/opt/pmux2shiftx.cc @@ -198,7 +198,7 @@ struct OnehotDatabase struct Pmux2ShiftxPass : public Pass { Pmux2ShiftxPass() : Pass("pmux2shiftx", "transform $pmux cells to $shiftx cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -225,7 +225,7 @@ struct Pmux2ShiftxPass : public Pass { log(" disable $sub inference for \"range decoders\"\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { int min_density = 50; int min_choices = 3; @@ -737,7 +737,7 @@ struct Pmux2ShiftxPass : public Pass { struct OnehotPass : public Pass { OnehotPass() : Pass("onehot", "optimize $eq cells for onehot signals") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -749,7 +749,7 @@ struct OnehotPass : public Pass { log(" verbose output\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool verbose = false; bool verbose_onehot = false; diff --git a/passes/opt/rmports.cc b/passes/opt/rmports.cc index 32363dd68..99a2a61c8 100644 --- a/passes/opt/rmports.cc +++ b/passes/opt/rmports.cc @@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN struct RmportsPassPass : public Pass { RmportsPassPass() : Pass("rmports", "remove module ports with no connections") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -39,7 +39,7 @@ struct RmportsPassPass : public Pass { log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing RMPORTS pass (remove ports with no connections).\n"); diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 988253edf..f7848e01d 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -1444,7 +1444,7 @@ struct ShareWorker struct SharePass : public Pass { SharePass() : Pass("share", "perform sat-based resource sharing") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1476,7 +1476,7 @@ struct SharePass : public Pass { log(" Only perform the first N merges, then stop. This is useful for debugging.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { ShareWorkerConfig config; diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index f60f2f8a8..8ce2fd478 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -482,7 +482,7 @@ struct WreduceWorker struct WreducePass : public Pass { WreducePass() : Pass("wreduce", "reduce the word size of operations if possible") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -505,7 +505,7 @@ struct WreducePass : public Pass { log(" Do not optimize explicit don't-care values.\n"); log("\n"); } - void execute(std::vector args, Design *design) YS_OVERRIDE + void execute(std::vector args, Design *design) override { WreduceConfig config; bool opt_memx = false; diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index f16cc4a0b..fff04074b 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -275,7 +275,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm) struct Ice40DspPass : public Pass { Ice40DspPass() : Pass("ice40_dsp", "iCE40: map multipliers") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -294,7 +294,7 @@ struct Ice40DspPass : public Pass { log("the accumulator to an arbitrary value can be inferred to use the {C,D} input.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing ICE40_DSP pass (map multipliers).\n"); diff --git a/passes/pmgen/ice40_wrapcarry.cc b/passes/pmgen/ice40_wrapcarry.cc index 97d2008c2..e234906ad 100644 --- a/passes/pmgen/ice40_wrapcarry.cc +++ b/passes/pmgen/ice40_wrapcarry.cc @@ -72,7 +72,7 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm) struct Ice40WrapCarryPass : public Pass { Ice40WrapCarryPass() : Pass("ice40_wrapcarry", "iCE40: wrap carries") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -91,7 +91,7 @@ struct Ice40WrapCarryPass : public Pass { log(" including restoring their attributes.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool unwrap = false; diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc index 4379ce1e6..c16b4486d 100644 --- a/passes/pmgen/peepopt.cc +++ b/passes/pmgen/peepopt.cc @@ -32,7 +32,7 @@ pool rminitbits; struct PeepoptPass : public Pass { PeepoptPass() : Pass("peepopt", "collection of peephole optimizers") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -41,7 +41,7 @@ struct PeepoptPass : public Pass { log("This pass applies a collection of peephole optimizers to the current design.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::string genmode; diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc index 9cfad03ef..7b2938ddf 100644 --- a/passes/pmgen/test_pmgen.cc +++ b/passes/pmgen/test_pmgen.cc @@ -118,7 +118,7 @@ void opt_eqpmux(test_pmgen_pm &pm) struct TestPmgenPass : public Pass { TestPmgenPass() : Pass("test_pmgen", "test pass for pmgen") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -239,7 +239,7 @@ struct TestPmgenPass : public Pass { log_cmd_error("Unknown pattern: %s\n", pattern.c_str()); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { if (GetSize(args) > 1) { diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index f1f4b4206..d05157270 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -744,7 +744,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm) struct XilinxDspPass : public Pass { XilinxDspPass() : Pass("xilinx_dsp", "Xilinx: pack resources into DSPs") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -785,7 +785,7 @@ struct XilinxDspPass : public Pass { log(" default: xc7\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing XILINX_DSP pass (pack resources into DSPs).\n"); diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index b99653fb3..1410850c7 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -188,7 +188,7 @@ void run_variable(xilinx_srl_pm &pm) struct XilinxSrlPass : public Pass { XilinxSrlPass() : Pass("xilinx_srl", "Xilinx shift register extraction") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -212,7 +212,7 @@ struct XilinxSrlPass : public Pass { log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing XILINX_SRL pass (Xilinx shift register extraction).\n"); diff --git a/passes/proc/proc.cc b/passes/proc/proc.cc index a5b4a3112..f20a167b4 100644 --- a/passes/proc/proc.cc +++ b/passes/proc/proc.cc @@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN struct ProcPass : public Pass { ProcPass() : Pass("proc", "translate processes to netlists") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -58,7 +58,7 @@ struct ProcPass : public Pass { log(" executed in -ifx mode.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::string global_arst; bool ifxmode = false; diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index e400fcb72..16db461b2 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -203,7 +203,7 @@ restart_proc_arst: struct ProcArstPass : public Pass { ProcArstPass() : Pass("proc_arst", "detect asynchronous resets") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -221,7 +221,7 @@ struct ProcArstPass : public Pass { log(" in the 'init' attribute on the net.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::string global_arst; bool global_arst_neg = false; diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 114c6ab03..5e78b7316 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -166,7 +166,7 @@ void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_count, bool struct ProcCleanPass : public Pass { ProcCleanPass() : Pass("proc_clean", "remove empty parts of processes") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -179,7 +179,7 @@ struct ProcCleanPass : public Pass { log("if it contains only empty structures.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { int total_count = 0; bool quiet = false; diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 59cc5bd65..e320a72a6 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -370,7 +370,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce) struct ProcDffPass : public Pass { ProcDffPass() : Pass("proc_dff", "extract flip-flops from processes") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -380,7 +380,7 @@ struct ProcDffPass : public Pass { log("d-type flip-flop cells.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing PROC_DFF pass (convert process syncs to FFs).\n"); diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index c9da1d1e3..e7c8a80dd 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -434,7 +434,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) struct ProcDlatchPass : public Pass { ProcDlatchPass() : Pass("proc_dlatch", "extract latches from processes") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -444,7 +444,7 @@ struct ProcDlatchPass : public Pass { log("d-type latches.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing PROC_DLATCH pass (convert process syncs to latches).\n"); diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index dc00019aa..eb323038d 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -86,7 +86,7 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc) struct ProcInitPass : public Pass { ProcInitPass() : Pass("proc_init", "convert initial block to init attributes") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -97,7 +97,7 @@ struct ProcInitPass : public Pass { log("respective wire.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing PROC_INIT pass (extract init attributes).\n"); diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 867ba1698..d20f34534 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -438,7 +438,7 @@ void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc, bool ifxmode) struct ProcMuxPass : public Pass { ProcMuxPass() : Pass("proc_mux", "convert decision trees to multiplexers") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -452,7 +452,7 @@ struct ProcMuxPass : public Pass { log(" 'case' expressions and 'if' conditions.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool ifxmode = false; log_header(design, "Executing PROC_MUX pass (convert decision trees to multiplexers).\n"); diff --git a/passes/proc/proc_prune.cc b/passes/proc/proc_prune.cc index 8d11447f6..bd122b91f 100644 --- a/passes/proc/proc_prune.cc +++ b/passes/proc/proc_prune.cc @@ -125,7 +125,7 @@ struct PruneWorker struct ProcPrunePass : public Pass { ProcPrunePass() : Pass("proc_prune", "remove redundant assignments") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -135,7 +135,7 @@ struct ProcPrunePass : public Pass { log("a later assignment to the same signal and removes them.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { int total_removed_count = 0, total_promoted_count = 0; log_header(design, "Executing PROC_PRUNE pass (remove redundant assignments in processes).\n"); diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index 6afaf25d1..ee91637ca 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -70,7 +70,7 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter, int &full_case_counter) struct ProcRmdeadPass : public Pass { ProcRmdeadPass() : Pass("proc_rmdead", "eliminate dead trees in decision trees") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -79,7 +79,7 @@ struct ProcRmdeadPass : public Pass { log("This pass identifies unreachable branches in decision trees and removes them.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n"); diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc index 5bf2296ab..e9a10465e 100644 --- a/passes/sat/assertpmux.cc +++ b/passes/sat/assertpmux.cc @@ -181,7 +181,7 @@ struct AssertpmuxWorker struct AssertpmuxPass : public Pass { AssertpmuxPass() : Pass("assertpmux", "adds asserts for parallel muxes") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -199,7 +199,7 @@ struct AssertpmuxPass : public Pass { log(" additional constraint and check the $pmux condition always.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool flag_noinit = false; bool flag_always = false; diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc index e344e2b5b..6fc480925 100644 --- a/passes/sat/async2sync.cc +++ b/passes/sat/async2sync.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct Async2syncPass : public Pass { Async2syncPass() : Pass("async2sync", "convert async FF inputs to sync circuits") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -42,7 +42,7 @@ struct Async2syncPass : public Pass { log("Currently only $adff, $dffsr, and $dlatch cells are supported by this pass.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { // bool flag_noinit = false; diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index 1e155e52c..e5c5d0486 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct Clk2fflogicPass : public Pass { Clk2fflogicPass() : Pass("clk2fflogic", "convert clocked FFs to generic $ff cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -36,7 +36,7 @@ struct Clk2fflogicPass : public Pass { log("multiple clocks.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { // bool flag_noinit = false; diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc index 26cc69211..2b310e0b4 100644 --- a/passes/sat/cutpoint.cc +++ b/passes/sat/cutpoint.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct CutpointPass : public Pass { CutpointPass() : Pass("cutpoint", "adds formal cut points to the design") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -38,7 +38,7 @@ struct CutpointPass : public Pass { log(" $anyseq cell and drive the cutpoint net from that\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool flag_undef = false; diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index f910ea80d..085e7c5b8 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -359,7 +359,7 @@ struct VlogHammerReporter struct EvalPass : public Pass { EvalPass() : Pass("eval", "evaluate the circuit given an input") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -382,7 +382,7 @@ struct EvalPass : public Pass { log(" then all output ports of the current module are used.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::vector> sets; std::vector shows, tables; diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 80ab82cd5..5fe7efc34 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -217,7 +217,7 @@ RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width struct ExposePass : public Pass { ExposePass() : Pass("expose", "convert internal signals to module ports") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -254,7 +254,7 @@ struct ExposePass : public Pass { log(" designator for the exposed signal.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool flag_shared = false; bool flag_evert = false; diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc index 5066485aa..5694a7473 100644 --- a/passes/sat/fmcombine.cc +++ b/passes/sat/fmcombine.cc @@ -235,7 +235,7 @@ struct FmcombineWorker struct FmcombinePass : public Pass { FmcombinePass() : Pass("fmcombine", "combine two instances of a cell into one") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -272,7 +272,7 @@ struct FmcombinePass : public Pass { log("If none of -fwd, -bwd, and -nop is given, then -fwd is used as default.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { opts_t opts; Module *module = nullptr; diff --git a/passes/sat/fminit.cc b/passes/sat/fminit.cc index 555a28dc6..c72e62548 100644 --- a/passes/sat/fminit.cc +++ b/passes/sat/fminit.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct FminitPass : public Pass { FminitPass() : Pass("fminit", "set init values/sequences for formal") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -47,7 +47,7 @@ struct FminitPass : public Pass { log(" Set clock for init sequences\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { vector>> initdata; vector> setdata; diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 5dfd7bd3f..762edfdfb 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -760,7 +760,7 @@ struct FreduceWorker struct FreducePass : public Pass { FreducePass() : Pass("freduce", "perform functional reduction") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -791,7 +791,7 @@ struct FreducePass : public Pass { log("circuit that is analyzed.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { reduce_counter = 0; reduce_stop_at = 0; diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index aeece9b94..fe4a819f3 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -354,7 +354,7 @@ void create_miter_assert(struct Pass *that, std::vector args, RTLIL struct MiterPass : public Pass { MiterPass() : Pass("miter", "automatically create a miter circuit") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -398,7 +398,7 @@ struct MiterPass : public Pass { log(" call 'flatten -wb; opt_expr -keepdc -undriven;;' on the miter circuit.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { if (args.size() > 1 && args[1] == "-equiv") { create_miter_equiv(this, args, design); diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc index af8ffca9e..15abee73e 100644 --- a/passes/sat/mutate.cc +++ b/passes/sat/mutate.cc @@ -726,7 +726,7 @@ void mutate_cnot(Design *design, const mutate_opts_t &opts, bool one) struct MutatePass : public Pass { MutatePass() : Pass("mutate", "generate or apply design mutations") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -790,7 +790,7 @@ struct MutatePass : public Pass { log(" Ignored. (They are generated by -list for documentation purposes.)\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { mutate_opts_t opts; string filename; diff --git a/passes/sat/qbfsat.cc b/passes/sat/qbfsat.cc index d6dbf8ef4..4686e985b 100644 --- a/passes/sat/qbfsat.cc +++ b/passes/sat/qbfsat.cc @@ -623,7 +623,7 @@ void print_qed() struct QbfSatPass : public Pass { QbfSatPass() : Pass("qbfsat", "solve a 2QBF-SAT problem in the circuit") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -690,7 +690,7 @@ struct QbfSatPass : public Pass { log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing QBFSAT pass (solving QBF-SAT problems in the circuit).\n"); QbfSolveOptions opt = parse_args(args); diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index e2fe5b846..d7bf125d1 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -893,7 +893,7 @@ void print_qed() struct SatPass : public Pass { SatPass() : Pass("sat", "solve a SAT problem in the circuit") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1060,7 +1060,7 @@ struct SatPass : public Pass { log(" Like -falsify but do not return an error for timeouts.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::vector> sets, sets_init, prove, prove_x; std::map>> sets_at; diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index 03ca42cf3..1ab082b09 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -751,7 +751,7 @@ struct SimWorker : SimShared struct SimPass : public Pass { SimPass() : Pass("sim", "simulate the circuit") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -793,7 +793,7 @@ struct SimPass : public Pass { log(" enable debug output\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { SimWorker worker; int numcycles = 20; diff --git a/passes/sat/supercover.cc b/passes/sat/supercover.cc index ba44f02d8..aacc044fb 100644 --- a/passes/sat/supercover.cc +++ b/passes/sat/supercover.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct SupercoverPass : public Pass { SupercoverPass() : Pass("supercover", "add hi/lo cover cells for each wire bit") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -35,7 +35,7 @@ struct SupercoverPass : public Pass { log("checking for a hi signal level and one checking for lo level.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { // bool flag_noinit = false; diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index fae8b2426..0a58fdcc0 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1276,7 +1276,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin struct AbcPass : public Pass { AbcPass() : Pass("abc", "use ABC for technology mapping") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1460,7 +1460,7 @@ struct AbcPass : public Pass { log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing ABC pass (technology mapping using ABC).\n"); log_push(); diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 06097a6f7..127f8934e 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -36,7 +36,7 @@ PRIVATE_NAMESPACE_BEGIN struct Abc9Pass : public ScriptPass { Abc9Pass() : ScriptPass("abc9", "use ABC9 for technology mapping") { } - void on_register() YS_OVERRIDE + void on_register() override { RTLIL::constpad["abc9.script.default"] = "+&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs"; RTLIL::constpad["abc9.script.default.area"] = "+&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs"; @@ -81,7 +81,7 @@ struct Abc9Pass : public ScriptPass "&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} {R} -v; &save; &load;"\ "&mfs"; } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -184,7 +184,7 @@ struct Abc9Pass : public ScriptPass int maxlut; std::string box_file; - void clear_flags() YS_OVERRIDE + void clear_flags() override { exe_cmd.str(""); exe_cmd << "abc9_exe"; @@ -195,7 +195,7 @@ struct Abc9Pass : public ScriptPass box_file = ""; } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::string run_from, run_to; clear_flags(); @@ -272,7 +272,7 @@ struct Abc9Pass : public ScriptPass log_pop(); } - void script() YS_OVERRIDE + void script() override { if (check_label("check")) { if (help_mode) diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index 0bf547921..7355840aa 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -293,7 +293,7 @@ void abc9_module(RTLIL::Design *design, std::string script_file, std::string exe struct Abc9ExePass : public Pass { Abc9ExePass() : Pass("abc9_exe", "use ABC9 for technology mapping") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -375,7 +375,7 @@ struct Abc9ExePass : public Pass { log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing ABC9_EXE pass (technology mapping using ABC9).\n"); diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 873c37b9a..9b69538e3 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -1530,7 +1530,7 @@ clone_lut: struct Abc9OpsPass : public Pass { Abc9OpsPass() : Pass("abc9_ops", "helper functions for ABC9") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1614,7 +1614,7 @@ struct Abc9OpsPass : public Pass { log(" inputs and outputs.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n"); diff --git a/passes/techmap/aigmap.cc b/passes/techmap/aigmap.cc index 2ecb2f35a..ce151c7f3 100644 --- a/passes/techmap/aigmap.cc +++ b/passes/techmap/aigmap.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct AigmapPass : public Pass { AigmapPass() : Pass("aigmap", "map logic to and-inverter-graph circuit") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -43,7 +43,7 @@ struct AigmapPass : public Pass { log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool nand_mode = false, select_mode = false; diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index 1925145d3..b16e9750e 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -550,7 +550,7 @@ struct AlumaccWorker struct AlumaccPass : public Pass { AlumaccPass() : Pass("alumacc", "extract ALU and MACC cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -560,7 +560,7 @@ struct AlumaccPass : public Pass { log("and $macc cells.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing ALUMACC pass (create $alu and $macc cells).\n"); diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc index 5f30817d4..8643543c8 100644 --- a/passes/techmap/attrmap.cc +++ b/passes/techmap/attrmap.cc @@ -81,7 +81,7 @@ struct AttrmapAction { struct AttrmapTocase : AttrmapAction { string name; - bool apply(IdString &id, Const&) YS_OVERRIDE { + bool apply(IdString &id, Const&) override { if (match_name(name, id, true)) id = RTLIL::escape_id(name); return true; @@ -90,7 +90,7 @@ struct AttrmapTocase : AttrmapAction { struct AttrmapRename : AttrmapAction { string old_name, new_name; - bool apply(IdString &id, Const&) YS_OVERRIDE { + bool apply(IdString &id, Const&) override { if (match_name(old_name, id)) id = RTLIL::escape_id(new_name); return true; @@ -101,7 +101,7 @@ struct AttrmapMap : AttrmapAction { bool imap; string old_name, new_name; string old_value, new_value; - bool apply(IdString &id, Const &val) YS_OVERRIDE { + bool apply(IdString &id, Const &val) override { if (match_name(old_name, id) && match_value(old_value, val, true)) { id = RTLIL::escape_id(new_name); val = make_value(new_value); @@ -113,7 +113,7 @@ struct AttrmapMap : AttrmapAction { struct AttrmapRemove : AttrmapAction { bool has_value; string name, value; - bool apply(IdString &id, Const &val) YS_OVERRIDE { + bool apply(IdString &id, Const &val) override { return !(match_name(name, id) && (!has_value || match_value(value, val))); } }; @@ -221,7 +221,7 @@ bool parse_attrmap_paramap_options(size_t &argidx, std::vector &arg struct AttrmapPass : public Pass { AttrmapPass() : Pass("attrmap", "renaming attributes") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -241,7 +241,7 @@ struct AttrmapPass : public Pass { log(" -imap keep=\"false\" keep=0 -remove keep=0\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing ATTRMAP pass (move or copy attributes).\n"); @@ -301,7 +301,7 @@ struct AttrmapPass : public Pass { struct ParamapPass : public Pass { ParamapPass() : Pass("paramap", "renaming cell parameters") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -317,7 +317,7 @@ struct ParamapPass : public Pass { log(" paramap -tocase INIT t:LUT4\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing PARAMAP pass (move or copy cell parameters).\n"); diff --git a/passes/techmap/attrmvcp.cc b/passes/techmap/attrmvcp.cc index e59aa6518..b3202c587 100644 --- a/passes/techmap/attrmvcp.cc +++ b/passes/techmap/attrmvcp.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct AttrmvcpPass : public Pass { AttrmvcpPass() : Pass("attrmvcp", "move or copy attributes from wires to driving cells") { } - void help() YS_OVERRIDE + void help() override { log("\n"); log(" attrmvcp [options] [selection]\n"); @@ -53,7 +53,7 @@ struct AttrmvcpPass : public Pass { log(" multiple times.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing ATTRMVCP pass (move or copy attributes).\n"); diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc index 3f4b6aa66..451325fee 100644 --- a/passes/techmap/clkbufmap.cc +++ b/passes/techmap/clkbufmap.cc @@ -35,7 +35,7 @@ void split_portname_pair(std::string &port1, std::string &port2) struct ClkbufmapPass : public Pass { ClkbufmapPass() : Pass("clkbufmap", "insert global buffers on clock networks") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -76,7 +76,7 @@ struct ClkbufmapPass : public Pass { modules_processed.insert(module); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing CLKBUFMAP pass (inserting global clock buffers).\n"); diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc index a7dce9c81..9a23cb90e 100644 --- a/passes/techmap/deminout.cc +++ b/passes/techmap/deminout.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct DeminoutPass : public Pass { DeminoutPass() : Pass("deminout", "demote inout ports to input or output") { } - void help() YS_OVERRIDE + void help() override { log("\n"); log(" deminout [options] [selection]\n"); @@ -33,7 +33,7 @@ struct DeminoutPass : public Pass { log("\"Demote\" inout ports to input or output ports, if possible.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing DEMINOUT pass (demote inout ports to input or output).\n"); diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc index aa9bbfe17..36e2854c0 100644 --- a/passes/techmap/dff2dffe.cc +++ b/passes/techmap/dff2dffe.cc @@ -253,7 +253,7 @@ struct Dff2dffeWorker struct Dff2dffePass : public Pass { Dff2dffePass() : Pass("dff2dffe", "transform $dff cells to $dffe cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -288,7 +288,7 @@ struct Dff2dffePass : public Pass { log(" $_DFFE_[NP]_.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing DFF2DFFE pass (transform $dff to $dffe where applicable).\n"); diff --git a/passes/techmap/dff2dffs.cc b/passes/techmap/dff2dffs.cc index c155297d9..1cb923445 100644 --- a/passes/techmap/dff2dffs.cc +++ b/passes/techmap/dff2dffs.cc @@ -26,7 +26,7 @@ PRIVATE_NAMESPACE_BEGIN struct Dff2dffsPass : public Pass { Dff2dffsPass() : Pass("dff2dffs", "process sync set/reset with SR over CE priority") { } - void help() YS_OVERRIDE + void help() override { log("\n"); log(" dff2dffs [options] [selection]\n"); @@ -39,7 +39,7 @@ struct Dff2dffsPass : public Pass { log(" output wire's init attribute (if any).\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing dff2dffs pass (merge synchronous set/reset into FF cells).\n"); diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc index 35645582b..c60a901c1 100644 --- a/passes/techmap/dffinit.cc +++ b/passes/techmap/dffinit.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct DffinitPass : public Pass { DffinitPass() : Pass("dffinit", "set INIT param on FF cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -54,7 +54,7 @@ struct DffinitPass : public Pass { log(" the already defined initial value.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing DFFINIT pass (set INIT param on FF cells).\n"); diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index aa344cf8a..6d1eaa7f8 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -549,7 +549,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare struct DfflibmapPass : public Pass { DfflibmapPass() : Pass("dfflibmap", "technology mapping of flip-flops") { } - void help() YS_OVERRIDE + void help() override { log("\n"); log(" dfflibmap [-prepare] -liberty [selection]\n"); @@ -565,7 +565,7 @@ struct DfflibmapPass : public Pass { log("liberty file.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n"); diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index f29044790..7278cb680 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -345,7 +345,7 @@ bool compareSortNeedleList(RTLIL::Module *left, RTLIL::Module *right) struct ExtractPass : public Pass { ExtractPass() : Pass("extract", "find subcircuits and replace them with cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -433,7 +433,7 @@ struct ExtractPass : public Pass { log("See 'help techmap' for a pass that does the opposite thing.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing EXTRACT pass (map subcircuits to cells).\n"); log_push(); diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index 77a4bc0b6..56b2ea584 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -760,7 +760,7 @@ void counter_worker( struct ExtractCounterPass : public Pass { ExtractCounterPass() : Pass("extract_counter", "Extract GreenPak4 counter cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -788,7 +788,7 @@ struct ExtractCounterPass : public Pass { log("\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing EXTRACT_COUNTER pass (find counters in netlist).\n"); diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index 9023d8687..3fcff01c3 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -539,7 +539,7 @@ struct ExtractFaWorker struct ExtractFaPass : public Pass { ExtractFaPass() : Pass("extract_fa", "find and extract full/half adders") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -561,7 +561,7 @@ struct ExtractFaPass : public Pass { log(" Verbose output\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { ExtractFaConfig config; diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc index 2d63e413f..07b4200cc 100644 --- a/passes/techmap/extract_reduce.cc +++ b/passes/techmap/extract_reduce.cc @@ -34,7 +34,7 @@ struct ExtractReducePass : public Pass ExtractReducePass() : Pass("extract_reduce", "converts gate chains into $reduce_* cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -63,7 +63,7 @@ struct ExtractReducePass : public Pass (cell->type == ID($_XOR_) && gt == GateType::Xor); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing EXTRACT_REDUCE pass.\n"); log_push(); diff --git a/passes/techmap/extractinv.cc b/passes/techmap/extractinv.cc index 269fe5c6c..9b350456f 100644 --- a/passes/techmap/extractinv.cc +++ b/passes/techmap/extractinv.cc @@ -35,7 +35,7 @@ void split_portname_pair(std::string &port1, std::string &port2) struct ExtractinvPass : public Pass { ExtractinvPass() : Pass("extractinv", "extract explicit inverter cells for invertible cell pins") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -57,7 +57,7 @@ struct ExtractinvPass : public Pass { log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing EXTRACTINV pass (extracting pin inverters).\n"); diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index a03226f9f..b5f55cffa 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -253,7 +253,7 @@ struct FlattenWorker struct FlattenPass : public Pass { FlattenPass() : Pass("flatten", "flatten design") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -270,7 +270,7 @@ struct FlattenPass : public Pass { log(" Ignore the 'whitebox' attribute on cell implementations.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing FLATTEN pass (flatten design).\n"); log_push(); diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index 72947237b..dfdbe6b88 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -1470,7 +1470,7 @@ static void split(std::vector &tokens, const std::string &text, cha struct FlowmapPass : public Pass { FlowmapPass() : Pass("flowmap", "pack LUTs with FlowMap") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1511,7 +1511,7 @@ struct FlowmapPass : public Pass { log(" explain decisions performed during depth relaxation.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { int order = 3; int minlut = 1; diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index 5aeb5ea79..b808a8d8e 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -55,7 +55,7 @@ void hilomap_worker(RTLIL::SigSpec &sig) struct HilomapPass : public Pass { HilomapPass() : Pass("hilomap", "technology mapping of constant hi- and/or lo-drivers") { } - void help() YS_OVERRIDE + void help() override { log("\n"); log(" hilomap [options] [selection]\n"); @@ -74,7 +74,7 @@ struct HilomapPass : public Pass { log(" each constant bit.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing HILOMAP pass (mapping to constant drivers).\n"); diff --git a/passes/techmap/insbuf.cc b/passes/techmap/insbuf.cc index 0686c0f2b..a3b5b698d 100644 --- a/passes/techmap/insbuf.cc +++ b/passes/techmap/insbuf.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct InsbufPass : public Pass { InsbufPass() : Pass("insbuf", "insert buffer cells for connected wires") { } - void help() YS_OVERRIDE + void help() override { log("\n"); log(" insbuf [options] [selection]\n"); @@ -37,7 +37,7 @@ struct InsbufPass : public Pass { log(" call to \"clean\" will remove all $_BUF_ in the design.)\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n"); diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index a18d02652..e8530a034 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -34,7 +34,7 @@ void split_portname_pair(std::string &port1, std::string &port2) struct IopadmapPass : public Pass { IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { } - void help() YS_OVERRIDE + void help() override { log("\n"); log(" iopadmap [options] [selection]\n"); @@ -97,7 +97,7 @@ struct IopadmapPass : public Pass { modules_processed.insert(module); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n"); diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc index 703bf6ff6..f56eff3e5 100644 --- a/passes/techmap/lut2mux.cc +++ b/passes/techmap/lut2mux.cc @@ -56,7 +56,7 @@ int lut2mux(Cell *cell) struct Lut2muxPass : public Pass { Lut2muxPass() : Pass("lut2mux", "convert $lut to $_MUX_") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -65,7 +65,7 @@ struct Lut2muxPass : public Pass { log("This pass converts $lut cells to $_MUX_ gates.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing LUT2MUX pass (convert $lut to $_MUX_).\n"); diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc index 3bb929009..43f2d97f5 100644 --- a/passes/techmap/maccmap.cc +++ b/passes/techmap/maccmap.cc @@ -365,7 +365,7 @@ PRIVATE_NAMESPACE_BEGIN struct MaccmapPass : public Pass { MaccmapPass() : Pass("maccmap", "mapping macc cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -375,7 +375,7 @@ struct MaccmapPass : public Pass { log("is used then the $macc cell is mapped to $add, $sub, etc. cells instead.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool unmap_mode = false; diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc index bd049d86d..24109b579 100644 --- a/passes/techmap/muxcover.cc +++ b/passes/techmap/muxcover.cc @@ -623,7 +623,7 @@ struct MuxcoverWorker struct MuxcoverPass : public Pass { MuxcoverPass() : Pass("muxcover", "cover trees of MUX cells with wider MUXes") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -656,7 +656,7 @@ struct MuxcoverPass : public Pass { log(" than different signals.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing MUXCOVER pass (mapping to wider MUXes).\n"); diff --git a/passes/techmap/nlutmap.cc b/passes/techmap/nlutmap.cc index 798d82248..e1ebfcad8 100644 --- a/passes/techmap/nlutmap.cc +++ b/passes/techmap/nlutmap.cc @@ -129,7 +129,7 @@ struct NlutmapWorker struct NlutmapPass : public Pass { NlutmapPass() : Pass("nlutmap", "map to LUTs of different sizes") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -149,7 +149,7 @@ struct NlutmapPass : public Pass { log("to generic logic gates ($_AND_, etc.).\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { NlutmapConfig config; diff --git a/passes/techmap/pmuxtree.cc b/passes/techmap/pmuxtree.cc index 2810b7f2d..b937d3fb0 100644 --- a/passes/techmap/pmuxtree.cc +++ b/passes/techmap/pmuxtree.cc @@ -67,7 +67,7 @@ static SigSpec recursive_mux_generator(Module *module, const SigSpec &sig_data, struct PmuxtreePass : public Pass { PmuxtreePass() : Pass("pmuxtree", "transform $pmux cells to trees of $mux cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -76,7 +76,7 @@ struct PmuxtreePass : public Pass { log("This pass transforms $pmux cells to trees of $mux cells.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing PMUXTREE pass.\n"); diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index d7a381e0a..237c261ae 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -403,7 +403,7 @@ struct ShregmapWorker struct ShregmapPass : public Pass { ShregmapPass() : Pass("shregmap", "map shift registers") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -461,7 +461,7 @@ struct ShregmapPass : public Pass { log(" map to greenpak4 shift registers.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { ShregmapOptions opts; string clkpol, enpol; diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 214157a64..3c78fbdbf 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -575,7 +575,7 @@ PRIVATE_NAMESPACE_BEGIN struct SimplemapPass : public Pass { SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -590,7 +590,7 @@ struct SimplemapPass : public Pass { log(" $sr, $ff, $dff, $dffsr, $adff, $dlatch\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing SIMPLEMAP pass (map simple cells to gate primitives).\n"); extra_args(args, 1, design); diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 535db9465..1cee51d06 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -991,7 +991,7 @@ struct TechmapWorker struct TechmapPass : public Pass { TechmapPass() : Pass("techmap", "generic technology mapper") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -1151,7 +1151,7 @@ struct TechmapPass : public Pass { log("essentially techmap but using the design itself as map library).\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing TECHMAP pass (map to technology primitives).\n"); log_push(); diff --git a/passes/techmap/tribuf.cc b/passes/techmap/tribuf.cc index 90f3a9d6f..79ddb4bd7 100644 --- a/passes/techmap/tribuf.cc +++ b/passes/techmap/tribuf.cc @@ -143,7 +143,7 @@ struct TribufWorker { struct TribufPass : public Pass { TribufPass() : Pass("tribuf", "infer tri-state buffers") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -160,7 +160,7 @@ struct TribufPass : public Pass { log(" to non-tristate logic. this option implies -merge.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { TribufConfig config; diff --git a/passes/techmap/zinit.cc b/passes/techmap/zinit.cc index 74604ba3b..c0faa1f31 100644 --- a/passes/techmap/zinit.cc +++ b/passes/techmap/zinit.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct ZinitPass : public Pass { ZinitPass() : Pass("zinit", "add inverters so all FF are zero-initialized") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -37,7 +37,7 @@ struct ZinitPass : public Pass { log(" also add zero initialization to uninitialized FFs\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool all_mode = false; diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc index 894610e2b..a7d51293d 100644 --- a/passes/tests/test_abcloop.cc +++ b/passes/tests/test_abcloop.cc @@ -244,7 +244,7 @@ static void test_abcloop() struct TestAbcloopPass : public Pass { TestAbcloopPass() : Pass("test_abcloop", "automatically test handling of loops in abc command") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -259,7 +259,7 @@ struct TestAbcloopPass : public Pass { log(" use this value as rng seed value (default = unix time).\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design*) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design*) override { int num_iter = 100; xorshift32_state = 0; diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc index 19f21493d..4ab46014d 100644 --- a/passes/tests/test_autotb.cc +++ b/passes/tests/test_autotb.cc @@ -327,7 +327,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s struct TestAutotbBackend : public Backend { TestAutotbBackend() : Backend("=test_autotb", "generate simple test benches") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -360,7 +360,7 @@ struct TestAutotbBackend : public Backend { log(" the current system time.\n"); log("\n"); } - void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override { int num_iter = 1000; int seed = 0; diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index c6801007d..942468e29 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -652,7 +652,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std:: struct TestCellPass : public Pass { TestCellPass() : Pass("test_cell", "automatically test the implementation of a cell type") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -712,7 +712,7 @@ struct TestCellPass : public Pass { log(" create a Verilog test bench to test simlib and write_verilog\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design*) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design*) override { int num_iter = 100; std::string techmap_cmd = "techmap -assert"; diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc index 262a5e700..ddd9822b9 100644 --- a/techlibs/achronix/synth_achronix.cc +++ b/techlibs/achronix/synth_achronix.cc @@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN struct SynthAchronixPass : public ScriptPass { SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Acrhonix Speedster22i FPGAs.") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -63,7 +63,7 @@ struct SynthAchronixPass : public ScriptPass { string top_opt, family_opt, vout_file; bool retime, flatten; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_opt = "-auto-top"; vout_file = ""; @@ -71,7 +71,7 @@ struct SynthAchronixPass : public ScriptPass { flatten = true; } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); @@ -118,7 +118,7 @@ struct SynthAchronixPass : public ScriptPass { log_pop(); } - void script() YS_OVERRIDE + void script() override { if (check_label("begin")) { diff --git a/techlibs/anlogic/anlogic_eqn.cc b/techlibs/anlogic/anlogic_eqn.cc index e4fa4413f..e5fbc186f 100644 --- a/techlibs/anlogic/anlogic_eqn.cc +++ b/techlibs/anlogic/anlogic_eqn.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct AnlogicEqnPass : public Pass { AnlogicEqnPass() : Pass("anlogic_eqn", "Anlogic: Calculate equations for luts") { } - void help() YS_OVERRIDE + void help() override { log("\n"); log(" anlogic_eqn [selection]\n"); @@ -63,7 +63,7 @@ struct AnlogicEqnPass : public Pass { return Const(eqn); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing ANLOGIC_EQN pass (calculate equations for luts).\n"); diff --git a/techlibs/anlogic/anlogic_fixcarry.cc b/techlibs/anlogic/anlogic_fixcarry.cc index f8e70260c..c7dfe3c05 100644 --- a/techlibs/anlogic/anlogic_fixcarry.cc +++ b/techlibs/anlogic/anlogic_fixcarry.cc @@ -98,7 +98,7 @@ static void fix_carry_chain(Module *module) struct AnlogicCarryFixPass : public Pass { AnlogicCarryFixPass() : Pass("anlogic_fixcarry", "Anlogic: fix carry chain") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -107,7 +107,7 @@ struct AnlogicCarryFixPass : public Pass { log("Add Anlogic adders to fix carry chain if needed.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing anlogic_fixcarry pass (fix invalid carry chain).\n"); diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc index 791dc922f..d7475df86 100644 --- a/techlibs/anlogic/synth_anlogic.cc +++ b/techlibs/anlogic/synth_anlogic.cc @@ -30,7 +30,7 @@ struct SynthAnlogicPass : public ScriptPass { SynthAnlogicPass() : ScriptPass("synth_anlogic", "synthesis for Anlogic FPGAs") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -72,7 +72,7 @@ struct SynthAnlogicPass : public ScriptPass string top_opt, edif_file, json_file; bool flatten, retime, nolutram; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_opt = "-auto-top"; edif_file = ""; @@ -82,7 +82,7 @@ struct SynthAnlogicPass : public ScriptPass nolutram = false; } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); @@ -137,7 +137,7 @@ struct SynthAnlogicPass : public ScriptPass log_pop(); } - void script() YS_OVERRIDE + void script() override { if (check_label("begin")) { diff --git a/techlibs/common/prep.cc b/techlibs/common/prep.cc index 82e6126c6..93b0910d6 100644 --- a/techlibs/common/prep.cc +++ b/techlibs/common/prep.cc @@ -29,7 +29,7 @@ struct PrepPass : public ScriptPass { PrepPass() : ScriptPass("prep", "generic synthesis script") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -81,7 +81,7 @@ struct PrepPass : public ScriptPass string top_module, fsm_opts; bool autotop, flatten, ifxmode, memxmode, nomemmode, nokeepdc, nordff; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_module.clear(); @@ -94,7 +94,7 @@ struct PrepPass : public ScriptPass nordff = true; } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { string run_from, run_to; @@ -163,7 +163,7 @@ struct PrepPass : public ScriptPass log_pop(); } - void script() YS_OVERRIDE + void script() override { if (check_label("begin")) diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index d6dffdd7f..b4c65e658 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -29,7 +29,7 @@ struct SynthPass : public ScriptPass { SynthPass() : ScriptPass("synth", "generic synthesis script") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -91,7 +91,7 @@ struct SynthPass : public ScriptPass bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap; int lut; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_module.clear(); fsm_opts.clear(); @@ -108,7 +108,7 @@ struct SynthPass : public ScriptPass abc = "abc"; } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); @@ -195,7 +195,7 @@ struct SynthPass : public ScriptPass log_pop(); } - void script() YS_OVERRIDE + void script() override { if (check_label("begin")) { diff --git a/techlibs/coolrunner2/coolrunner2_fixup.cc b/techlibs/coolrunner2/coolrunner2_fixup.cc index 8bbff9ba5..50710e2bd 100644 --- a/techlibs/coolrunner2/coolrunner2_fixup.cc +++ b/techlibs/coolrunner2/coolrunner2_fixup.cc @@ -112,7 +112,7 @@ RTLIL::Wire *makeptermbuffer(RTLIL::Module *module, SigBit inwire) struct Coolrunner2FixupPass : public Pass { Coolrunner2FixupPass() : Pass("coolrunner2_fixup", "insert necessary buffer cells for CoolRunner-II architecture") { } - void help() YS_OVERRIDE + void help() override { log("\n"); log(" coolrunner2_fixup [options] [selection]\n"); @@ -120,7 +120,7 @@ struct Coolrunner2FixupPass : public Pass { log("Insert necessary buffer cells for CoolRunner-II architecture.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing COOLRUNNER2_FIXUP pass (insert necessary buffer cells for CoolRunner-II architecture).\n"); extra_args(args, 1, design); diff --git a/techlibs/coolrunner2/coolrunner2_sop.cc b/techlibs/coolrunner2/coolrunner2_sop.cc index 045c73978..17e0d8432 100644 --- a/techlibs/coolrunner2/coolrunner2_sop.cc +++ b/techlibs/coolrunner2/coolrunner2_sop.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct Coolrunner2SopPass : public Pass { Coolrunner2SopPass() : Pass("coolrunner2_sop", "break $sop cells into ANDTERM/ORTERM cells") { } - void help() YS_OVERRIDE + void help() override { log("\n"); log(" coolrunner2_sop [options] [selection]\n"); @@ -33,7 +33,7 @@ struct Coolrunner2SopPass : public Pass { log("Break $sop cells into ANDTERM/ORTERM cells.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing COOLRUNNER2_SOP pass (break $sop cells into ANDTERM/ORTERM cells).\n"); extra_args(args, 1, design); diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc index d5eeaf547..47102fbb1 100644 --- a/techlibs/coolrunner2/synth_coolrunner2.cc +++ b/techlibs/coolrunner2/synth_coolrunner2.cc @@ -29,7 +29,7 @@ struct SynthCoolrunner2Pass : public ScriptPass { SynthCoolrunner2Pass() : ScriptPass("synth_coolrunner2", "synthesis for Xilinx Coolrunner-II CPLDs") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -66,7 +66,7 @@ struct SynthCoolrunner2Pass : public ScriptPass string top_opt, json_file; bool flatten, retime; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_opt = "-auto-top"; json_file = ""; @@ -74,7 +74,7 @@ struct SynthCoolrunner2Pass : public ScriptPass retime = false; } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); @@ -121,7 +121,7 @@ struct SynthCoolrunner2Pass : public ScriptPass log_pop(); } - void script() YS_OVERRIDE + void script() override { if (check_label("begin")) { diff --git a/techlibs/easic/synth_easic.cc b/techlibs/easic/synth_easic.cc index b4a3a1ac9..897bc1c40 100644 --- a/techlibs/easic/synth_easic.cc +++ b/techlibs/easic/synth_easic.cc @@ -29,7 +29,7 @@ struct SynthEasicPass : public ScriptPass { SynthEasicPass() : ScriptPass("synth_easic", "synthesis for eASIC platform") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -67,7 +67,7 @@ struct SynthEasicPass : public ScriptPass string top_opt, vlog_file, etools_path; bool flatten, retime; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_opt = "-auto-top"; vlog_file = ""; @@ -76,7 +76,7 @@ struct SynthEasicPass : public ScriptPass retime = false; } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); @@ -127,7 +127,7 @@ struct SynthEasicPass : public ScriptPass log_pop(); } - void script() YS_OVERRIDE + void script() override { string phys_clk_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_phys_clk_0v893ff125c.lib", etools_path.c_str()); string logic_lut_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_logic_lut_0v893ff125c.lib", etools_path.c_str()); diff --git a/techlibs/ecp5/ecp5_ffinit.cc b/techlibs/ecp5/ecp5_ffinit.cc index ba72bd0c6..0ecc86388 100644 --- a/techlibs/ecp5/ecp5_ffinit.cc +++ b/techlibs/ecp5/ecp5_ffinit.cc @@ -26,7 +26,7 @@ PRIVATE_NAMESPACE_BEGIN struct Ecp5FfinitPass : public Pass { Ecp5FfinitPass() : Pass("ecp5_ffinit", "ECP5: handle FF init values") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -36,7 +36,7 @@ struct Ecp5FfinitPass : public Pass { log("If reset is not used, set the reset value to the init value, otherwise\n"); log("unmap out the reset (if not an async reset).\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing ECP5_FFINIT pass (implement FF init values).\n"); diff --git a/techlibs/ecp5/ecp5_gsr.cc b/techlibs/ecp5/ecp5_gsr.cc index 3d3f8e1c1..18d99cfb2 100644 --- a/techlibs/ecp5/ecp5_gsr.cc +++ b/techlibs/ecp5/ecp5_gsr.cc @@ -26,7 +26,7 @@ PRIVATE_NAMESPACE_BEGIN struct Ecp5GsrPass : public Pass { Ecp5GsrPass() : Pass("ecp5_gsr", "ECP5: handle GSR") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -40,7 +40,7 @@ struct Ecp5GsrPass : public Pass { log("is not set, otherwise it will be resolved to \"DISABLED\".\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing ECP5_GSR pass (implement FF init values).\n"); diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index aceb36abc..c9451e76b 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -30,12 +30,12 @@ struct SynthEcp5Pass : public ScriptPass { SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { } - void on_register() YS_OVERRIDE + void on_register() override { RTLIL::constpad["synth_ecp5.abc9.W"] = "300"; } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -112,7 +112,7 @@ struct SynthEcp5Pass : public ScriptPass string top_opt, blif_file, edif_file, json_file; bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, nodsp, vpr; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_opt = "-auto-top"; blif_file = ""; @@ -133,7 +133,7 @@ struct SynthEcp5Pass : public ScriptPass nodsp = false; } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); @@ -239,7 +239,7 @@ struct SynthEcp5Pass : public ScriptPass log_pop(); } - void script() YS_OVERRIDE + void script() override { if (check_label("begin")) { diff --git a/techlibs/efinix/efinix_fixcarry.cc b/techlibs/efinix/efinix_fixcarry.cc index 1a1733a17..486b8e89c 100644 --- a/techlibs/efinix/efinix_fixcarry.cc +++ b/techlibs/efinix/efinix_fixcarry.cc @@ -90,7 +90,7 @@ static void fix_carry_chain(Module *module) struct EfinixCarryFixPass : public Pass { EfinixCarryFixPass() : Pass("efinix_fixcarry", "Efinix: fix carry chain") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -99,7 +99,7 @@ struct EfinixCarryFixPass : public Pass { log("Add Efinix adders to fix carry chain if needed.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing EFINIX_FIXCARRY pass (fix invalid carry chain).\n"); diff --git a/techlibs/efinix/efinix_gbuf.cc b/techlibs/efinix/efinix_gbuf.cc index 55dfb3c79..ae191359a 100644 --- a/techlibs/efinix/efinix_gbuf.cc +++ b/techlibs/efinix/efinix_gbuf.cc @@ -87,7 +87,7 @@ static void handle_gbufs(Module *module) struct EfinixGbufPass : public Pass { EfinixGbufPass() : Pass("efinix_gbuf", "Efinix: insert global clock buffers") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -96,7 +96,7 @@ struct EfinixGbufPass : public Pass { log("Add Efinix global clock buffers to top module as needed.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing efinix_gbuf pass (insert global clock buffers).\n"); diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc index f9a7ef865..6ca44eed1 100644 --- a/techlibs/efinix/synth_efinix.cc +++ b/techlibs/efinix/synth_efinix.cc @@ -30,7 +30,7 @@ struct SynthEfinixPass : public ScriptPass { SynthEfinixPass() : ScriptPass("synth_efinix", "synthesis for Efinix FPGAs") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -72,7 +72,7 @@ struct SynthEfinixPass : public ScriptPass string top_opt, edif_file, json_file; bool flatten, retime, nobram; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_opt = "-auto-top"; edif_file = ""; @@ -82,7 +82,7 @@ struct SynthEfinixPass : public ScriptPass nobram = false; } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); @@ -137,7 +137,7 @@ struct SynthEfinixPass : public ScriptPass log_pop(); } - void script() YS_OVERRIDE + void script() override { if (check_label("begin")) { diff --git a/techlibs/gowin/determine_init.cc b/techlibs/gowin/determine_init.cc index 18a64e451..15ff115de 100644 --- a/techlibs/gowin/determine_init.cc +++ b/techlibs/gowin/determine_init.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct DetermineInitPass : public Pass { DetermineInitPass() : Pass("determine_init", "Determine the init value of cells") { } - void help() YS_OVERRIDE + void help() override { log("\n"); log(" determine_init [selection]\n"); @@ -44,7 +44,7 @@ struct DetermineInitPass : public Pass { return init; } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing DETERMINE_INIT pass (determine init value for cells).\n"); diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index dd965c0b8..9a3106729 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -29,7 +29,7 @@ struct SynthGowinPass : public ScriptPass { SynthGowinPass() : ScriptPass("synth_gowin", "synthesis for Gowin FPGAs") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -82,7 +82,7 @@ struct SynthGowinPass : public ScriptPass string top_opt, vout_file; bool retime, nobram, nolutram, flatten, nodffe, nowidelut, abc9, noiopads; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_opt = "-auto-top"; vout_file = ""; @@ -96,7 +96,7 @@ struct SynthGowinPass : public ScriptPass noiopads = false; } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); @@ -167,7 +167,7 @@ struct SynthGowinPass : public ScriptPass log_pop(); } - void script() YS_OVERRIDE + void script() override { if (check_label("begin")) { diff --git a/techlibs/greenpak4/greenpak4_dffinv.cc b/techlibs/greenpak4/greenpak4_dffinv.cc index 62057318b..b8797bc19 100644 --- a/techlibs/greenpak4/greenpak4_dffinv.cc +++ b/techlibs/greenpak4/greenpak4_dffinv.cc @@ -91,7 +91,7 @@ void invert_gp_dff(Cell *cell, bool invert_input) struct Greenpak4DffInvPass : public Pass { Greenpak4DffInvPass() : Pass("greenpak4_dffinv", "merge greenpak4 inverters and DFF/latches") { } - void help() YS_OVERRIDE + void help() override { log("\n"); log(" greenpak4_dffinv [options] [selection]\n"); @@ -99,7 +99,7 @@ struct Greenpak4DffInvPass : public Pass { log("Merge GP_INV cells with GP_DFF* and GP_DLATCH* cells.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing GREENPAK4_DFFINV pass (merge input/output inverters into FF/latch cells).\n"); diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc index bfbb56d15..17b5d4782 100644 --- a/techlibs/greenpak4/synth_greenpak4.cc +++ b/techlibs/greenpak4/synth_greenpak4.cc @@ -29,7 +29,7 @@ struct SynthGreenPAK4Pass : public ScriptPass { SynthGreenPAK4Pass() : ScriptPass("synth_greenpak4", "synthesis for GreenPAK4 FPGAs") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -70,7 +70,7 @@ struct SynthGreenPAK4Pass : public ScriptPass string top_opt, part, json_file; bool flatten, retime; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_opt = "-auto-top"; part = "SLG46621V"; @@ -79,7 +79,7 @@ struct SynthGreenPAK4Pass : public ScriptPass retime = false; } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); @@ -133,7 +133,7 @@ struct SynthGreenPAK4Pass : public ScriptPass log_pop(); } - void script() YS_OVERRIDE + void script() override { if (check_label("begin")) { diff --git a/techlibs/ice40/ice40_braminit.cc b/techlibs/ice40/ice40_braminit.cc index 936c189ea..e5d1f7e24 100644 --- a/techlibs/ice40/ice40_braminit.cc +++ b/techlibs/ice40/ice40_braminit.cc @@ -128,7 +128,7 @@ static void run_ice40_braminit(Module *module) struct Ice40BRAMInitPass : public Pass { Ice40BRAMInitPass() : Pass("ice40_braminit", "iCE40: perform SB_RAM40_4K initialization from file") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -138,7 +138,7 @@ struct Ice40BRAMInitPass : public Pass { log("parameter and converts it into the required INIT_x attributes\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing ICE40_BRAMINIT pass.\n"); diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc index d7715135e..2eef3fa93 100644 --- a/techlibs/ice40/ice40_ffinit.cc +++ b/techlibs/ice40/ice40_ffinit.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct Ice40FfinitPass : public Pass { Ice40FfinitPass() : Pass("ice40_ffinit", "iCE40: handle FF init values") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -35,7 +35,7 @@ struct Ice40FfinitPass : public Pass { log("nonzero init values.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing ICE40_FFINIT pass (implement FF init values).\n"); diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc index ffb8c74b1..492029b77 100644 --- a/techlibs/ice40/ice40_ffssr.cc +++ b/techlibs/ice40/ice40_ffssr.cc @@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN struct Ice40FfssrPass : public Pass { Ice40FfssrPass() : Pass("ice40_ffssr", "iCE40: merge synchronous set/reset into FF cells") { } - void help() YS_OVERRIDE + void help() override { log("\n"); log(" ice40_ffssr [options] [selection]\n"); @@ -33,7 +33,7 @@ struct Ice40FfssrPass : public Pass { log("Merge synchronous set/reset $_MUX_ cells into iCE40 FFs.\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).\n"); diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 18c1a58cf..1a70fa8c0 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -203,7 +203,7 @@ static void run_ice40_opts(Module *module) struct Ice40OptPass : public Pass { Ice40OptPass() : Pass("ice40_opt", "iCE40: perform simple optimizations") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -220,7 +220,7 @@ struct Ice40OptPass : public Pass { log(" while \n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { string opt_expr_args = "-mux_undef -undriven"; diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 27850b075..f2fc1ca6d 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -29,14 +29,14 @@ struct SynthIce40Pass : public ScriptPass { SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { } - void on_register() YS_OVERRIDE + void on_register() override { RTLIL::constpad["synth_ice40.abc9.hx.W"] = "250"; RTLIL::constpad["synth_ice40.abc9.lp.W"] = "400"; RTLIL::constpad["synth_ice40.abc9.u.W"] = "750"; } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -119,7 +119,7 @@ struct SynthIce40Pass : public ScriptPass bool nocarry, nodffe, nobram, dsp, flatten, retime, noabc, abc2, vpr, abc9, dff, flowmap; int min_ce_use; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_opt = "-auto-top"; blif_file = ""; @@ -140,7 +140,7 @@ struct SynthIce40Pass : public ScriptPass device_opt = "hx"; } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); @@ -262,7 +262,7 @@ struct SynthIce40Pass : public ScriptPass log_pop(); } - void script() YS_OVERRIDE + void script() override { std::string define; if (device_opt == "lp") diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 8601ebb37..f3709498c 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN struct SynthIntelPass : public ScriptPass { SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { experimental(); } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -81,7 +81,7 @@ struct SynthIntelPass : public ScriptPass { string top_opt, family_opt, vout_file, blif_file; bool retime, flatten, nobram, iopads; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_opt = "-auto-top"; family_opt = "max10"; @@ -93,7 +93,7 @@ struct SynthIntelPass : public ScriptPass { iopads = false; } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); @@ -163,7 +163,7 @@ struct SynthIntelPass : public ScriptPass { log_pop(); } - void script() YS_OVERRIDE + void script() override { if (check_label("begin")) { if (check_label("family")) diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index 6508affc0..fabfc9003 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -29,7 +29,7 @@ PRIVATE_NAMESPACE_BEGIN struct SynthIntelALMPass : public ScriptPass { SynthIntelALMPass() : ScriptPass("synth_intel_alm", "synthesis for ALM-based Intel (Altera) FPGAs.") {} - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -74,7 +74,7 @@ struct SynthIntelALMPass : public ScriptPass { string top_opt, family_opt, bram_type, vout_file; bool flatten, quartus, nolutram, nobram; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_opt = "-auto-top"; family_opt = "cyclonev"; @@ -86,7 +86,7 @@ struct SynthIntelALMPass : public ScriptPass { nobram = false; } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); @@ -153,7 +153,7 @@ struct SynthIntelALMPass : public ScriptPass { log_pop(); } - void script() YS_OVERRIDE + void script() override { if (help_mode) { family_opt = ""; diff --git a/techlibs/sf2/sf2_iobs.cc b/techlibs/sf2/sf2_iobs.cc index 619888d38..5fd719ce5 100644 --- a/techlibs/sf2/sf2_iobs.cc +++ b/techlibs/sf2/sf2_iobs.cc @@ -155,7 +155,7 @@ static void handle_clkint(Module *module) struct Sf2IobsPass : public Pass { Sf2IobsPass() : Pass("sf2_iobs", "SF2: insert IO buffers") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -167,7 +167,7 @@ struct Sf2IobsPass : public Pass { log(" Insert PAD->global_net clock buffers\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { bool clkbuf_mode = false; diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc index 34a7e68be..6b2a3f9b8 100644 --- a/techlibs/sf2/synth_sf2.cc +++ b/techlibs/sf2/synth_sf2.cc @@ -29,7 +29,7 @@ struct SynthSf2Pass : public ScriptPass { SynthSf2Pass() : ScriptPass("synth_sf2", "synthesis for SmartFusion2 and IGLOO2 FPGAs") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -78,7 +78,7 @@ struct SynthSf2Pass : public ScriptPass string top_opt, edif_file, vlog_file, json_file; bool flatten, retime, iobs, clkbuf; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_opt = "-auto-top"; edif_file = ""; @@ -90,7 +90,7 @@ struct SynthSf2Pass : public ScriptPass clkbuf = false; } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); @@ -153,7 +153,7 @@ struct SynthSf2Pass : public ScriptPass log_pop(); } - void script() YS_OVERRIDE + void script() override { if (check_label("begin")) { diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index d0de73f83..a0d6c279a 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -30,13 +30,13 @@ struct SynthXilinxPass : public ScriptPass { SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { } - void on_register() YS_OVERRIDE + void on_register() override { RTLIL::constpad["synth_xilinx.abc9.xc7.W"] = "300"; // Number with which ABC will map a 6-input gate // to one LUT6 (instead of a LUT5 + LUT2) } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -149,7 +149,7 @@ struct SynthXilinxPass : public ScriptPass int lut_size; int widelut_size; - void clear_flags() YS_OVERRIDE + void clear_flags() override { top_opt = "-auto-top"; edif_file.clear(); @@ -176,7 +176,7 @@ struct SynthXilinxPass : public ScriptPass lut_size = 6; } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { std::string run_from, run_to; clear_flags(); @@ -337,7 +337,7 @@ struct SynthXilinxPass : public ScriptPass log_pop(); } - void script() YS_OVERRIDE + void script() override { std::string lut_size_s = std::to_string(lut_size); if (help_mode) diff --git a/techlibs/xilinx/xilinx_dffopt.cc b/techlibs/xilinx/xilinx_dffopt.cc index c9d63c9f7..365f505fb 100644 --- a/techlibs/xilinx/xilinx_dffopt.cc +++ b/techlibs/xilinx/xilinx_dffopt.cc @@ -99,7 +99,7 @@ bool merge_lut(LutData &result, const LutData &data, const LutData select, bool struct XilinxDffOptPass : public Pass { XilinxDffOptPass() : Pass("xilinx_dffopt", "Xilinx: optimize FF control signal usage") { } - void help() YS_OVERRIDE + void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); @@ -113,7 +113,7 @@ struct XilinxDffOptPass : public Pass { log(" Assume a LUT4-based device (instead of a LUT6-based device).\n"); log("\n"); } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing XILINX_DFFOPT pass (optimize FF control signal usage).\n"); diff --git a/tests/various/plugin.cc b/tests/various/plugin.cc index be305fbda..451484c50 100644 --- a/tests/various/plugin.cc +++ b/tests/various/plugin.cc @@ -4,7 +4,7 @@ YOSYS_NAMESPACE_BEGIN struct TestPass : public Pass { TestPass() : Pass("test", "test") { } - void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + void execute(std::vector args, RTLIL::Design *design) override { size_t argidx = 1; extra_args(args, argidx, design); -- 2.30.2