From 719b81f0d133a1c9c5647e5da285234216453c6c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 18 Sep 2022 15:22:27 +0100 Subject: [PATCH] reword prohibited "silicon partner" --- openpower/sv/rfc/ls001.mdwn | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn index 2076a9529..d9ebd84a7 100644 --- a/openpower/sv/rfc/ls001.mdwn +++ b/openpower/sv/rfc/ls001.mdwn @@ -120,14 +120,14 @@ the catastrophic side-effect of introducing not only binary incompatibility but silent data corruption as well as no means to trap-and-emulate differing bitwidths.[^vsx256] -Thus "Silicon-Partner" Scalability +"Silicon-Partner" Scalability is identical to mixing 32-bit Power ISA +with 64-bit in the same binary (just as catastrophic), and is prohibited in the Simple-V Scalable Vector ISA, -This does -mean that `RESERVED` space is crucial to have, in order -to safely provide the option of +`RESERVED` space is thus crucial to have, in order +to provide the option of future expanded register file bitwidths and sizes[^msr], -under explicitly-distinguishable encoding, -**at the discretion of and with the full authority of the OPF ISA WG**, +under **explicitly-distinguishable** encoding, +**at the discretion of the OPF ISA WG**, not the implementor ("Silicon Partner"). # Hardware Implementations -- 2.30.2